V V U | Intel MCS-80/85 specification

FUNCTIONAL DESCRIPTION

logical choices, since they both force the pro- cessor to push the contents of the program counter onto the stack before jumping to a new location. In Figure 2-17it is assumed that a CALL opcode is sent to the CPU during M1• The CALL opcode could have been placed there bya device like the 8259 programmable interrupt controller.

After receiving the opcode, the processor then decodes it and determines, in this case, that the CALL instruction requires two more bytes. The CPU therefore performs a second INA cycle (M2) to access the second byte of the instruction from the 8259. The timing of this cycle is iden- tical to M1, except that it has only three .T states. M2 is followed by another INA cycle (M3) to access the third byte of the CALL instruction from the 8259.

Now that the CPU has accessed the entire in- struction used to acknowledge the interrupt, it will execute that instruction.. Note that any in- struction could be used (except EI or 01, the in-· structions which enable or disable interrupts), but the RESTART and CALL instructions are the most logical choices. Also notice that the CPU inhibited the incrementing of the program counter (PC) during the three INA cycles, so that the correct PC value can be pushed onto the stack during M4 and M5'

During M4 and Ms, the CPU performs MEMORY WRITE machine cycles to write the upper and then lower bytes of the PC onto the top of the stack. The CPU then places the two bytes ac- c,essed in M2 and M3 into the lower and upper bytes of the PC. This has the effect of jumping the execution of the program to the location specified by the CALL instruction.

		M3 (INA)			M4(MW)			MS(MW)			Ml (OF)
SIGNAL
	Tl	T2	T3	Tl	T2	T3	Tl	T2	T3	Tl	T2

ClK

V V

V'lJ'V V

V V V V U-

INTR

-

1 ---

INTA

\\

[X

oc

D<

X

IOIM,Sl,SO

(1,1,1)

(0,0,1)

(0,0,1)

(0,1,1)

[X

X

AS·A1S

IX

)(

PCH

(SP·l)H

(SP·2)H

PCH(B3)

OUT

IN

OUT

OUT

OUT

OUT

OUT

k=:

E

E

K::K

AO ·A0

X 00

.07 (B3)

>

0 .0

7

(PCH)

0

0

.0

7

(PCL)

O 7

0

"

L

ALE

r\

Jf\.

V\

AD

WR

FIGURE 2·18INTERRUPT ACKNOWLEDGE MACHINE CYCLES (WITH CALL INSTRUCTION IN RESPONSE TO INTR)

2·14

Image 37

Intel MCS-80/85 manual V V U

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.

Contents

Page Inter INTEl Corporation Table of Contents Page Introduction Page Chapter Part 1 Introduction to Functions of a Computer Instruction Register and Decoder Program Counter Jumps, Subroutines and the Stack Address Registers Control CircuitryArithmetic/Logic Unit ALU Timing Memory Read Instruction FetchMemory Write Wait memory synchronization Module Evolution MCS·SS Microcomputer System Introduction to MCS-85 Software Compatibility 8155 =CE, 8156 =CE MCS·S5 Special Peripheral Components ·1. MCS·SS Basic System Programmable Peripherals Interfacing to MCS·80/8S Programmable Peripheral ComponentsMEMil. lOR Demultiplexing the BUS Interfacing to Standard Memory System Performance Instruction CYCLE/ACCESS TimeDistributed Processing Conclusions THROUGHPUT/COSTPage Functional Description Page Whatsin the 808SA ·1 808SA CPU Functional Block Diagram Hexidecimal Binary AEH Hexadecimalbinary A7H122H ·28085A Clock Logic ·38085A Hardware and SOFT· Ware RST Branch Locations ·5RIM Read Interrupt Mask ·4INTERRUPT Masks SET Using SIM Instruction Name Priority When Inter· Rupt occursType Branched to ·8BASIC CPU Functions HOW the MCS·85SYSTEM Works ·9 CPU Timing for Store Accumulator Direct STA Instruction Functional Description ·12808SA Machine State Chart ·13OPCODE Fetch Machine Cycle of DCX Instruction Lililili Memory Write MW Jl..Jl..Jl..J LIl..Jl..J ~ U- U-U V V U Lr \F LrLrU-U-U-U- U ~--r \J li\ Lr V V- U V u u u U ·21 Hold VS Interrupt NON Halt RST 5.5 Mask Resets SetsRST 6~5 Mask RST 7.5 Mask 7J==- 10ms.c = ~ ALE Signals Function AS-AI5 101M =x---C Conclusion Page System Operating Page LOA MvimSTA Lhld Address Assignment System Operation To , , I X X X Memory·Mapped ·-·-1 Interfacing to Standard BUS Memories Interfacing to MCS·80 PeripheralsDynamic RAM Interface ·3 MCS·80 Peripherals with 110 Mapped Parts Functions Minimum MCS-85 System T1t Scale =11 System Operation ·8 Expanded System Parts Function System Operation Expanded MCS·85 SystemROM/EPROM CPUPage Functional Description Page Chapter 8080 Central Processor Unit Registers Instruction Register and Control Arithmetic and Logic Unit ALUData Bus Buffer Machine Cycle Identification State Transition Sequence Status Bit Definitions $ no Irr\ RL- rL- rL.-h rL-h -h rL-rL- r-L State Associated Activities LnLn IrL Hold Sequences ~ ~ ~~ w---t. ~~u----t Wl ~ ~ Page Page Page Page Condition Iiii Instruction Set Page H,SP H,L000 B 011 E 100 H Instruction and Data Formats LabelData Word \JNN Condition Flags Addressing Modes Instruction SET Encyclopedia O o 1 1 o Instruction SET ADD M XchgP,CY,AC R CY ~-1 ~-· «H L P,AC8085, 5 \ r DAA00 0 S S S Address,jng Cleared RLC ORA M CMC CMA1 1 1 1 Condition «SP Cycles 2/5 8085,315 States 9/18 8085, 11/17 Flag Word PchlPop 1 0 16 8085, 18 RIM NOP SIM 8085A 8080Al8085A Instruction SET Index Sossa 808SA 808SA Instruction SET Summary Contd Device Specifications Page Inter Inter Absolute Maximum RATINGS· LC~ Wait Inter 8080Al8080A·1/8080A·2 Waveforms Data and Instruction Formats Instruction Set Summary Inter8080Al8080A·118080A·2 Inter8080A/8080A·1/8080A·2 8085AH Pin AH CPU Functional Block Diagram Configuration 8085AH/8085AH-2/8085AH-1 Interrupt Priority, Restart Address, and Sensitivity Pin DescriptionVee Interrupt and Serial 1/0 Driving the X1 and X2 Inputs MHz Input Frequency External Clock Quartz Crystal Clock DriverDriver Circuit LC Tuned Circuit Clock Driver RiD~ 001 AH Basic System Timing AH Machine State Chart SOS5AH/SOS5AH-2/S0S5AH-1 Absolute Maximum RATINGS· 8085AH/8085AH-2/8085AH-1 Characteristics 8085AH 8085AH-2 8085AH-1 Bus Timing Specification as a Teye Dependent Symbol TlDW 8085AH/8085AH-2/8085AH-1 Waveforms IntJ 8085AH/8085AH-2/8085AH-1 I8085AH/8085AH-2/8085AH-1 SA Pin CPU Functional Block Diagram = ov ±5%, Vss = OV unless otherwise specified Absolute Maximum Ratings ClK low Time Standard ClK loading TCYC ClK Cycle Period 320 2000120 Tnt ClK Rise and Fall Time TXKR Rising to ClK Rising Xi Rising to ClK Falling 150 Ready Setup Time to leading Edge Symbol Parameter 8085A2 8085A·22 Units Min MaxTrailing Edge of Read to Re·Enabling Address TRD Read or Inta to Valid DataPage Appendix Page Appendix AP.PLICATIONS of MCS-85 Baud Rates MCS-85 Applications 111J RLm LlL R14 PAt8~~P Additional 808SA Interrupts 64K 16K 32KMemory Addressing As an example letslook at IntelsROM/EPROM family Fig Ihl YT~~ Static Memories EJ EJ EJ Data DMA Direct Memory AccessRefresh D5H During initializationA4H LXI Sp =11 System Timings OT~ ·2Clock Related Timing Vs MHz Considerations 2T-80 Minimum System Memory Device Compatibility Address access TAD MEM Chip select access AddreS? access TAD MEM Chip select accessOutput enable TRD MEM BOSSA, A-2Memory Compatibility Bus Compatibility Analysis see Figure Gates Ns ea Flip Flop Return path 2 8216s CAS path from ALE Bus Compatibility Analysis see Contd TDHR 160 nsGates Flip Flops 15 ns 8216s 30 ns Flip flop 41 ns 200 10p,A Input Current TIL single load 40p,A 6mA Schottky or HtilTIL + 36 MOS Schotiky or 1 Htil Application Example 333 1 D1 Software Temperature Sensor Flow Diagram ~.,.-~ Thermistor Resistance Mapping JNZ search Has the entireReturn Clear HL CRT Interface RS·232C Interface Schematic Fi1 Output Routine POP !? PP-lHALFPrT HOi + 6 =HO = 01H Bf?E Cassette Recorder Interface One Chip Magnetic Tape Interface Schematic BLl2 ButT01 ~1V! A..OCeH FeNO Bf1 JC TIl Additional Comments A1·43 Temperature Sensor Code Temperature Sensor Code Contd Temperature Sensor Code Contd Temperature Sensor Code Contd CRT and Cassette Code E81B ?EceBRm Ep! l 08,.1 ES77 C2760S 102 \/1ES7A Le? E87B C2760S 104 06e9 SEce3E01 RERn Eight Opta ens 0911 C2OC99 9914 C9TI2 TIl . Repeat Until Full BrTE ASSEt-18LEr Tu30B BlnIN a ,38 Eurcd a€18F2 089E BITSr ErTINBtl RRcrPage Workshops Page Experience Intel Workshops Chicago Area Boston AreaDallas Area SAN Francisco BAY Area Lab sessions on SDK-8S System Design Kit Introduction to Microprocessors MCS-80/85 Microprocessors Domestic Sales Offices IntJ ~9Jf69rt,~~9 \.,1 Inter Service Offices