Intel MCS-80/85 manual Pin Description, Interrupt Priority, Restart Address, and Sensitivity, Vee

intJ				8085AH/8085AH-2/8085AH-1
				Table 1. Pin Description (Continued)
, ------- , ----- , ---------------------- ,
Symbol		Type	Name and Function			Symbol		Type		Name and Function
TRAP		I	Trap: Trap	interrupt is a non-	RESET OUT			a		Reset Out: Reset Out indicates cpu
			maskable RESTART interrupt. It is							is being reset. Can be used
			recognized at the same time as							as a system reset. The signal is
			INTR or RST 5.5-7.5. It is unaffected							synchronized to the processor
			by any mask or Interrupt Enable. It							clock and lasts an integral number
			has the highest priority of any inter-							of clock periods.
			rupt. (See Table 2.)
					X1 ,X2			I		X 1 and X2: Are connected to a
			Reset In: Sets the Program
										crystal, le, or RC network to drive
			Counter to zero and resets the Inter-							the internal clock generator. X1 can
			rupt Enable and HlDA flip-flops.							also be an external clock input from
			The data and address buses and the							a logic gate. The input frequency is
			control lines are 3-stated during							divided by 2 to give the processor's
			RESET and because of the asyn-							internal operating frequency.
			chronous nature of RESET, the pro-
					ClK			a		Clock: Clock output for use as a sys-
			cessor'sinternal registers and flags
										tem clock. The period of ClK is
			may be altered by RESET with un-
										twice the X1 , X2 input period.
			predictable results. RESET IN is a
					SID			I		Serial Input Data Line: The data on
			Schmitt-triggered input, allowing
			connection to an R-C network for							this line is loaded into accumulator
			power-on RESET delay (see Figure							bit 7 whenever a RIM instruction is
			3). Upon power-up, RESET IN must							executed.
			remain low for at least 10 ms after		SOD			a		Serial Output Data Line: The out-
			minimum Vee has been reached.							put SOD is set or reset as specified
			For proper reset operation after the							by the SIM instruction.
			power-up duration, RESET IN
					Vee					Power:	+5 volt supply.
			should be kept Iowa minimum of
			three clock periods. The CPU is held		Vss					Ground:	Reference.
			in the reset condition as long as
			RESET IN is applied.
			Table 2. Interrupt Priority, Restart Address, and Sensitivity
				Address Branched To (1)
	Name		Priority	When Interrupt Occurs					Type Trigger
	TRAP		1	24H			Rising edge AND high level until sampled.
	RST 7.5		2	3CH			Rising edge (latched).
	RST 6.5		3	34H			High level until sampled.
	RST 5.5		4	2CH			High level until sampled.
	INTR		5	See Note 121.			High level until sampled.

NOTES:

1.The processor pushes the PC on the stack before branching to the indicated address.

2.The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.

	c~1	c,	TYPICAL POWER-ON RESET RC VALUES'
		I~
vee 0			Rl = 75Kn
			Cl =1 !iF
			'VALUESMAY HAVE TO VARY DUETO
			APPLIED POWER SUPPLY RAMP UP TIME.

Figure 3. Power-On Reset Circuit

i1\1"

I

:1

6-12 AFN·01835C