Intel MCS-80/85 manual HOW the MCS·85SYSTEM Works, ·8BASIC CPU Functions

FUNCTIONAL DESCRIPTION

2.3HOW THE MCS·85SYSTEM WORKS

The 8085A CPU generates signals that tell peripheral devices what type of information is 9n the multiplexed Address/Data bus and from that point on the operation is almost identical to the MCS-80™ CPU Group. A multiplexed bus structure was chosen because it freed device pins so that more functions could be integrated on the 8085A and other components of the fami- ly. The multiplexed bus is designed to allow complete compatibility to existing peripheral

components with improved timing margins and access requirements. (See Figure 2-8.)

To enhance the system integration of MCS-85, several special components with combined memory and I/O were designed. These new devices directly interface to the multiplexed bus of the 8085A. The pin locations of the 8085A and the special peripheral components are assigned to minimize PC board area and to allow for efficient layout. The details on peripheral components are contained in subse- quent paragraphs of this chapter and in Chapters 5 and 6.

			ADDRESS BUS
		SOSSA	_ ALE
		1 ---
INTR - ·	----	I	MULTIPLEXED
INTA -----	<II
			ADDRESS/DATA BUS
-------- I		IC> ---	AD
RESET IN	10 ---	WR
RESET OUT ------- I		1 ----	IO/M

FIGURE 2·SAMC8-S0™ cPU GROUP	FIGURE 2·SBMCS·S5™ cPU/SOS5A (MCS-SO COMPATIBLE
	FUNCTIONS)

DATA/ADDRESS BUS

==)(__A7_.AO_...JX___~_·D_o__L
ADDRESS	DATA IN OR OUT

TIME MULTIPLEX DATA BUS

FIGURE 2·SC MULTIPLEXED BUS TIMING

FIGURE 2·8BASIC CPU FUNCTIONS

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