Intel MCS-80/85 manual System Timings

SYSTEM TIMINGS

808SA elK-IN vs. ClK-OUT vs. Control Timings

This section shows timing characteristics that relate the input clock to the control signals and the output clock. These timings can be treated as constants, that is, within the normal opera- tive range of the processor, they are cycle or SOS5A, A-2 speed independent.

Be careful about manipulating the timings given in this section with the specifications in the data sheet. The specifications on the SOS5A, A-2 are not mutually exclusive; that is, you can'tadd minimums to minimums and obtain a valid mini- mum for some other timing parameter. Where the timing parameter is specified directly, this takes precedence over any other method you come up with to find that specification (through adding and subtracting others). This was not done to confuse the user, but to provide him with the most optimal timings for his system!

To understand the timing parameters in this section it would be helpful to understand how the internal signals are generated in the SOS5A. Referring to Figure 13, it is

seen that the rising edge of the X1 input causes flip·flop A to toggle. From this flip-flop two internal signals are generated that drive all functions in the SOS5A, A-2 and produce the output control signals and clock. Referring to Figure 15, it is seen that clock output is derived from the internal <1>1 signal in the schematic of Figure 14. This output Signal is a MOS output unlike the bipolar outputs of the S224 in the SOSOA system. This restricts the user to the loading limitations of a MOS driver (for further details see bus loading section). The rest ofthe output control signals with their respective internal controlling edges are also shown in Figure 14.

Since the path between the X1 input and the clock out- put can have a considerable amount of variance, the relationships of these two clocks vary significantly. Figures 15 and 16 are a set of timing diagrams il- lustrating the relationship of the clock input to the clock output to the various control signals. For designs that require these relationships to synchronize different systems, components, etc; the designer must allow for these variances in the rel3tionships.

Parameter	Description	Min	Max	Units
t</>AL	Time from C.F. to next Address valid (Ao - A7)		130	ns
t</>ALU	Time from C.F. to next Address valid (AS - A15 only)		70	ns
t</>AT	Time from C.F. to present Address remaining valid (AS - A15 only)	-20		ns
t</>CL	Time from C.F. to control low (L.E.)	-10	60	ns
t</>CT	Time from C.R. to control low (T.E.)	-10	60	ns
t</>OL	Time from C.F. to Data Out becoming valid		65	ns
t</>OT	Time from C.F. to Data Out remaining valid	-20		ns
t</>os	Data-in set up time to C.R.	100		ns
t</>OH	Data-in hold time to C.R.	0		ns
t</>LL	Time from C.F. to ALE high (L.E.)	-60	0	ns
t</>LT	Time from C.R. to ALE high (T.E.)	0	70	ns
tXKF	Time from X1 input to C.F.	30	150	ns
tXKR	Time from X1 input to C.R.	30	120	ns

C.F. = Clock Falling, C.R. = Clock Rising, L.E. = Leading Edge, T.E. = Trailing Edge

NOTE: These numbers are guaranteed by design and are not tested by Intel.

808SA, 808SA-2 Clock Parameters

OTHER INTERNAL

L~

Figure 13. Clock and Sample Control Logic

TRI-STATE CONTROL

A1-16