Intel MCS-80/85 manual ·4INTERRUPT Masks SET Using SIM Instruction, ·5RIM Read Interrupt Mask

FUNCTIONAL DESCRIPTION

Iii,'.I

Ii

instruction, which enables or disables thes.e in- terrupts by clearing or setting corresponding mask flags based on data in the accumulator. (See Figure 2-4.) You may read the status of the interrupt mask previously set by peforming a RIM instruction. Its execution loads into the ac- cumulator the following information. (See Figure 2-5.)

•Current interrupt mask status for the RST 5.5,6.5, and 7.5 hardware status.

•Current interrupt enable flag status (ex- cept that immediately following TRAP, the IE flag status preceding that inter- rupt is loaded).

•RST 5.5,6.5, and 7.5 interrupts pending.

RST 5.5, 6.5, and 7.5 are also subject to being enabled or disabled by the EI and 01 instruc- tions, respectively. INTR, RST 5.5, and RST 6.5 are level-sensitive, meaning that these inputs may be acknowledged by the processor when they are held at a high level. RST 7.5 is edge- sensitive, meaning that an internal flip-flop in the BOB5A registers the occurrence of an inter- rupt the instant a rising edge appears on the RST 7.5 input line. This input need not be held high; the flip-flop will remain set until it is cleared by one of three possible actions:

•The BOB5A responds to the interrupt, and sends an internal reset signal to the RST 7.5 flip-flop. (See Figure 2-6A.)

I

I

I

I

I

I

SIM - SET INTERRUPT MASK		RST 7.5
(OPCODE = 30)			!SET	808SA I
CONTENTS OF ACCUMULATOR BEFORE EXECUTING SIM:
		IRy~51'		(IN~~~A~
RESET INTERRUPT 7.5	I	INTERRUPT
	INTERRUPT MASKS
FLlp·FlOP		REQUEST
		(INTERNAL)
MASK SET ENABLE

FIGURE 2·6ARST 7.5 FLIP FLOP

FIGURE 2·4INTERRUPT MASKS SET USING
SIM INSTRUCTION					8085A
				TRAP
			REsET1iii
						SCHMIIT
						TRIGGER
							RESET
								+5V
	RIM - READ INTERRUPT MASK					ClK			D ClK
	(OPCODE = 20)									Q
									o
	CONTENTS OF ACCUMULATOR AFTER EXECUTING RIM:								F/F
									CLEAR
									TRAP F.F.
						INTERNAL
							TRAP
						ACKNOWLEDGE
	I	I
	PENDING INTERRUPTS	INTERRUPT MASKS

FIGURE 2·68TRAP INTERRUPT INPUTS

TRAP

INTERRUPT

REQUEST

(INTERNAL)

INTERRUPT ENABLE FLAG

FIGURE 2·5RIM - READ INTERRUPT MASK	FIGURE 2·6 RST 7.5 AND TRAP INTERRUPT
	INPUTS

2-4