FUNCTIONAL DESCRIPTION

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instruction, which enables or disables thes.e in- terrupts by clearing or setting corresponding mask flags based on data in the accumulator. (See Figure 2-4.) You may read the status of the interrupt mask previously set by peforming a RIM instruction. Its execution loads into the ac- cumulator the following information. (See Figure 2-5.)

Current interrupt mask status for the RST 5.5,6.5, and 7.5 hardware status.

Current interrupt enable flag status (ex- cept that immediately following TRAP, the IE flag status preceding that inter- rupt is loaded).

RST 5.5,6.5, and 7.5 interrupts pending.

RST 5.5, 6.5, and 7.5 are also subject to being enabled or disabled by the EI and 01 instruc- tions, respectively. INTR, RST 5.5, and RST 6.5 are level-sensitive, meaning that these inputs may be acknowledged by the processor when they are held at a high level. RST 7.5 is edge- sensitive, meaning that an internal flip-flop in the BOB5A registers the occurrence of an inter- rupt the instant a rising edge appears on the RST 7.5 input line. This input need not be held high; the flip-flop will remain set until it is cleared by one of three possible actions:

The BOB5A responds to the interrupt, and sends an internal reset signal to the RST 7.5 flip-flop. (See Figure 2-6A.)

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SIM - SET INTERRUPT MASK

 

RST 7.5

 

(OPCODE = 30)

 

 

!SET

808SA I

CONTENTS OF ACCUMULATOR BEFORE EXECUTING SIM:

 

 

 

 

IRy~51'

(IN~~~A~

RESET INTERRUPT 7.5

 

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INTERRUPT

 

 

 

 

INTERRUPT MASKS

 

FLlp·FlOP

 

 

REQUEST

 

 

 

 

 

 

 

 

(INTERNAL)

 

MASK SET ENABLE

 

 

 

 

FIGURE 2·6ARST 7.5 FLIP FLOP

FIGURE 2·4INTERRUPT MASKS SET USING

 

 

 

 

 

 

 

 

SIM INSTRUCTION

 

 

 

8085A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRAP

 

 

 

 

 

 

 

 

 

 

 

REsET1iii

 

 

 

 

 

 

 

 

 

 

 

 

SCHMIIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRIGGER

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

+5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIM - READ INTERRUPT MASK

 

ClK

 

D ClK

 

 

 

 

 

 

 

 

(OPCODE = 20)

 

 

 

 

 

 

 

 

 

Q

 

 

 

 

 

 

 

 

 

 

 

o

 

 

CONTENTS OF ACCUMULATOR AFTER EXECUTING RIM:

 

 

 

 

 

F/F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLEAR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRAP F.F.

 

 

 

 

 

 

INTERNAL

 

 

 

 

 

 

 

TRAP

 

 

 

 

 

 

ACKNOWLEDGE

 

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PENDING INTERRUPTS

INTERRUPT MASKS

 

 

 

 

 

 

 

 

FIGURE 2·68TRAP INTERRUPT INPUTS

TRAP

INTERRUPT

REQUEST

(INTERNAL)

INTERRUPT ENABLE FLAG

FIGURE 2·5RIM - READ INTERRUPT MASK

FIGURE 2·6 RST 7.5 AND TRAP INTERRUPT

INPUTS

2-4

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Image 27
Intel MCS-80/85 manual ·4INTERRUPT Masks SET Using SIM Instruction, ·5RIM Read Interrupt Mask

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.