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Intel MCS-80/85 manual Signals Function, Ale

Models: MCS-80/85

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FUNCTIONAL DESCRIPTION

MCS·80™ System Bus

The MCS-80 bus is terminated on one end by the CPU-GROUP (consisting of the 8080A, 8224, 8228) and on the other end by the various memory and 1/0 circuits. The following figure shows the major signals of the MCS-80 bus.

MCS·85™ System Bus

The MCS-85 bus is terminated on one end by the 8085A and the other end by various memory and 1/0 devices. The MCS-85 bus may be optionally de-multiplexed with an 8212 eight bit latch to provide an MCS-80 type bus. The following figure shows the major signals of the MCS-85 bus.

INT

INTA

HOLD

HlDA

READY

RESET q,2(TIl)

8080A

8224

8228

16 Ao-A,s

l'

• 0

 

-0

7

i 8

0

 

 

MEMR, MEMW lOR, lOW

INTR

INTA

HOLD

HlDA

READY RESET OUT elK

SOS5A

mEt, -- 1 (0 -18212

8

8AS -A 1S

 

 

8

ADo-AD7

 

 

 

 

 

/

 

RD,WR

 

 

4

 

 

101M,

~lE

 

 

 

FIGURE 2·27COMPARISON OF SYSTEM BUSES

MCS·80™ System Bus

MCS·85™ System Bus

SIGNAL(S)

FUNCTION

SIGNAL(S)

FUNCTION

The 16 lines of the address bus identify a memory or 1/0 location for a data transfer operation.

The 8 lines of the data bus are used for the parallel transfer of data between two devices.

MEMR, MEMW, These five control lines lOR, lOW, INTA (MEMORY READ, MEMORY WRITE, 1/0 READ, 1/0 WRITE, and INTERRUPT ACKNOWL- EDGE) identify the type and timing of a data transfer

operation.

READY, RESET, These signals are used for

HOlD,HlDA the synchronization of slow

cJ>2 (TTl), INT speed memories, system reset, DMA, sytem timing, and CPU interrupt.

FIGURE 2·28COMPARISON OF SYSTEM BUSES

These are the high order eight bits of the address, and are used to identify a memory or I/O location for a data transfer cycle.

These eight lines serve a dual function. During the beginning of a data transfer operation, these lines carry the low order eight bits of the address bus. During the remainder of the cycle, these lines are used for the parallel transfer of data be- tween two devices.

 

These signals identify the

 

type and timing of a data

 

transfer cycle.

101M

The I/OIMEMORY line iden-

 

tifies a data transfer as be-

 

ing in the I/O address space

 

or the memory address

 

space.

ALE

ADDRESS lATCH ENABLE

 

enables the latching of the

 

Ao-A7 signals.

READY, RESET These signals are used for

OUT, HOLD, the synchronization of slow HlDA, elK, INTR speed memories, system reset, DMA, system timing

and CPU interrupt.

2-21

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Intel MCS-80/85 manual Signals Function, Ale
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MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.