SYSTEM OPERATION

devices in the system, which would force them to be either ones or zeroes. Remember that two devices may not be selected simultaneously; thus each device must have an address that not only selects itself, but also deselects all other devices. If there are any bits which are truly "don'tcares," they are customarily assigned to be zero. If all the "X" bits in Figure 3.1A were "don'tcares," then the chip could be addressed as memory locations 0-2k, and 1/0 Ports 0-3.

Figure 3.1 B shows a slightly larger system of two 8355s and one 8156. Notice that 8355 No.1 uses its two chip enable lines to decode A12 = 1,

A13 = O. It is possible to address each of the chips without selecting any of the others. Also

notice that there are some illegal addresses (e.g., A12 =0, A13 =1) that would cause two of the devices to turn on simultaneously. The pro- grammer must not use these addresses.

Figure 3.1C shows a larger MCS-85 system. Two 8205s are used to completely decode the ad- dresses. There are some interesting points to observe here. First, while some of the devices have multiple possible address (Le., they have some "don'tcare" bits), there aren'tany ad- dresses which can cause simultaneous selec- tion of two or more parts. Second, the 1/0 and

memory portions of the 8x55 components share chip enables, so they are forced to live with each other'sconstraints. Third, only one 8205 is required per eight chips for the decoding; that's an overhead of only 1/8 of a chip per part.

Figure 3.1 D shows a remedy to the problem il- lustrated in Figure 3.1 C, namely that I/O and memory portions of the chip are forced to live with each other'schip enable constraints. By using a quad 2 to 1 multiplexer, the chip enables of the I/O and memory portions of four chips can be independently assigned.

3.4.2Memory·Mapped 110:

Figure 3.2A shows all 8355 connected to the 8085A. Since the 101M pin of the 8355 is con- nected to A15, whenever A15 = 1 the 1/0 ports will be accessed. While A15 could be set to 1 either by a memory or by an I/O instruction, in this situation the port is usually accessed only by the memory instructions. You may access ports either as memory locations (where A15 = 1 refers to a memory address of 32k or higher) or as 1/0 ports (where A15 = 1 refers to an 110 ad- dress of 128 or higher, since bits Aa-A15 are a

FIGURE 3·2ASINGLE CHIP

 

 

 

 

 

 

 

 

 

8355/8755A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A,, --------- tCE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

vee----~CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A'5--------- tIO/M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

X I0

MEMORY ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

X

A,o'

. I·

.

. . I·

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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1/0 ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

X

X

xlo

X ·-·-1-

 

 

 

X A,Aol

FIGURE 3·2BMULTIPLE CHIPS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8156

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

101M

 

 

 

 

 

 

 

 

MEMORY ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8355/8755A

 

 

 

l lox 1

1 IX X

X X IA 7 -

.

. I.

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

 

 

 

 

 

1/0 ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

11

X 1 11X X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

 

. .

I· .

.

. I X

A2 A, Aol

 

 

 

 

 

 

 

 

101M

 

 

 

 

 

 

 

 

 

 

 

8355/8755A

 

 

 

 

 

 

 

11 x

MEMORY ADDRESS

-1- .

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

IO

 

X

0

Ala-

-1- ..

Aol

 

 

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CE

 

 

 

 

 

 

 

 

 

 

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" ---

101M

 

-

 

 

{ 11

 

X

0 1IX X .

·1-

- .

. I· X

A,

Aol

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MEMORY ADDRESS

 

" " "'I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1:

X

0

0 I 'A,,"

"I"

" " "I"

 

 

 

 

 

 

 

 

 

 

 

 

 

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{

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIGURE 3-2 MC8-8S™ PERIPHERALS WITH MEMORY-MAPPED 1/0

3-4

Page 52 Page 54
Page 53
Image 53
Intel MCS-80/85 manual ·-·-1, Memory·Mapped
Page 52 Page 54

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.
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