intJ 8085AH/8085AH-2/8085AH-1

II',

I.'

I

I"

BASIC SYSTEM TIMING

The 8085AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 10 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/O write and read cycle that the I/O port address is copied on both the upper and lower half of the address.

There are seven possible types of machine cycles. Which of these seven takes plac~ is defined by the status of the three status lines (IO/M, S1, So) and the three control signals (RD, WR, and INTA). (See Table 3.) The status lines can be used as advanced con- trols (for device selection, for example), since they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR become active later, at the time when the transfer of data is to take place, so are used as command lines.

A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which nor- mally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 4.

Table 3. 8085AH Machine Cycle Chart

MACHINE CYCLE

 

STATUS

 

CONTROL

 

 

 

 

 

 

 

 

101M

S1

so

RD

WR

 

INTA

OPCODE FETCH

(OF)

0

1

1

0

1

 

1

MEMORY READ

(MR)

0

1

0

0

1

 

1

MEMORY WRITE

(MW)

0

0

1

1

0

 

1

1/0 READ

(lOR)

1

1

0

0

1

 

1

I/OWRITE

(lOW)

1

0

1

1

0

 

1

ACKNOWLEDGE

 

 

 

 

 

 

 

 

OFINTR

(INA)

1

1

1

1

1

 

0

BUS IDLE

(BI): DAD

0

1

0

1

1

 

1

 

ACK.OF

 

 

 

 

 

 

 

 

RST,TRAP

1

1

1

1

1

 

1

 

HALT

TS

0

0

TS

TS

 

1

 

 

 

 

 

 

 

 

 

Table 4. 8085AH Machine State Chart

 

 

 

 

Status & Buses

 

 

Control

 

 

Machine

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

101M

 

 

 

 

 

 

 

Ro,WR

INTA

ALE

 

 

 

 

 

 

 

 

 

 

State

S1.S0

 

As-A15

 

 

 

ADo-AD7

T,

 

X

X

 

X

 

 

 

 

X

1

 

1

 

1"

T2

 

X

X

 

X

 

 

 

 

X

X

 

X

 

0

 

 

 

 

 

 

 

 

TWAIT

 

X

X

 

X

 

 

 

 

X

X

 

X

 

0

T3

 

X

X

 

X

 

 

 

 

X

X

 

X

 

0

T4

 

1

 

0'

 

X

 

 

 

 

TS

1

 

1

 

0

 

 

 

 

 

 

 

 

 

T5

 

1

 

0'

 

X

 

 

 

TS

1

 

1

 

0

 

 

 

 

Ts

 

1

 

o t

I

X

 

 

 

TS

1

 

1

 

0

 

 

I

 

 

 

 

 

TRESET

 

X

TS

 

TS

 

 

 

TS

TS

 

1

 

0

I

 

 

 

 

 

 

THALT

I

0

 

TS

 

TS

 

 

 

TS

TS

 

1

I

0

 

 

 

 

 

 

 

 

THOLD

 

X

TS

 

TS

 

TS

TS

 

1

 

0

0= logic "0"

 

 

 

TS = High Impedance

 

 

 

 

 

, = logic "'"

 

 

 

 

x = Unspecified

 

 

 

 

 

*ALE not generated during 2nd and 3rd machine cycles of DAD instruction.

t101M = , during T4-T6of INA machine cycle.

I'!I

I,

I'I

I)

I

I

I'

I·,

ClK

T,

 

 

 

 

 

 

PCH (HIGH ORDER ADDRESS)

PC l

~----

(LOW ORDER

DATA FROM

ADDRESS)

 

MEMORY

 

 

(INSTRUCTION)

ALE

WR

S,So (FETCH)10 (READ)01 WRITEl'

Figure 10. 8085AH Basic System Timing

6-18

AFN·01835C

Page 126 Page 128
Page 127
Image 127
Intel MCS-80/85 manual AH Machine State Chart, AH Basic System Timing
Page 126 Page 128

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.
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