Intel MCS-80/85 manual AH Machine State Chart, AH Basic System Timing

intJ 8085AH/8085AH-2/8085AH-1

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BASIC SYSTEM TIMING

The 8085AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 10 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/O write and read cycle that the I/O port address is copied on both the upper and lower half of the address.

There are seven possible types of machine cycles. Which of these seven takes plac~ is defined by the status of the three status lines (IO/M, S1, So) and the three control signals (RD, WR, and INTA). (See Table 3.) The status lines can be used as advanced con- trols (for device selection, for example), since they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR become active later, at the time when the transfer of data is to take place, so are used as command lines.

A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which nor- mally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 4.

Table 3. 8085AH Machine Cycle Chart

MACHINE CYCLE		STATUS			CONTROL
		101M	S1	so	RD	WR	INTA
OPCODE FETCH	(OF)	0	1	1	0	1	1
MEMORY READ	(MR)	0	1	0	0	1	1
MEMORY WRITE	(MW)	0	0	1	1	0	1
1/0 READ	(lOR)	1	1	0	0	1	1
I/OWRITE	(lOW)	1	0	1	1	0	1
ACKNOWLEDGE
OFINTR	(INA)	1	1	1	1	1	0
BUS IDLE	(BI): DAD	0	1	0	1	1	1
	ACK.OF
	RST,TRAP	1	1	1	1	1	1
	HALT	TS	0	0	TS	TS	1

Table 4. 8085AH Machine State Chart

Status & Buses

Control

Machine

101M

Ro,WR

INTA

ALE

State

S1.S0

As-A15

ADo-AD7

T,

X

X

X

X

1

1

1"

T2

X

X

X

X

X

X

0

TWAIT

X

X

X

X

X

X

0

T3

X

X

X

X

X

X

0

T4

1

0'

X

TS

1

1

0

T5

1

0'

X

TS

1

1

0

Ts

1

o t

I

X

TS

1

1

0

I

TRESET

X

TS

TS

TS

TS

1

0

I

THALT

I

0

TS

TS

TS

TS

1

I

0

THOLD

X

TS

TS

TS

TS

1

0

0= logic "0"

TS = High Impedance

, = logic "'"

x = Unspecified

*ALE not generated during 2nd and 3rd machine cycles of DAD instruction.

t101M = , during T4-T6of INA machine cycle.

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ClK T,

PCH (HIGH ORDER ADDRESS)

PC l	~----
(LOW ORDER		DATA FROM
ADDRESS)		MEMORY
		(INSTRUCTION)

ALE

WR

S,So (FETCH)10 (READ)01 WRITEl'

Figure 10. 8085AH Basic System Timing

6-18 AFN·01835C