\--TONE BURST---I

VOH

@lUI

VOL

®

3V

'-..r\.J

1V

@GND ------ ,

( RECORDING OR TRANSMISSION MEDIUM)

+1V

@GND----~

-1V

@2 . 0V -----

GND

CD 2 . 0V ---- _

GND

+4V

~

@ 2.0V

\ , \

I k::::::: COMPARATOR

~LEVEL

W

 

L

GND ____-- '

, • RECONSTRUCTED SIGNAL .,

Figure 27. Analog Signal Waveforms

After the CRT software analysis, the tape routines are almost trivial. TAPEO is a subroutine for out- putting the contents of register C to a cassette recorder. TAPEIN reads 8 bits into register C.

OUTPUT ROUTINE

TAPEO calls a subroutine named BURST three times for each bit. If A6 (the SOD enable bit) is set when BURST is called, a square-wave tone burst will be transmitted. If A6 is not set, BURST simply delays for exactly the same amount of time before returning. The three calls are used to, respectively, output the initial burst, output the data burst/space, and create the space at the end of each bit. Nine bits will be output: the eight data bits (LSB first) followed by a zero bit. The start of the initial burst of the trailing zero is needed to mark the end of the final space of the preceding data bit.

Start each bit by outputting a tone burst:

TAPEI]: 1'1'.11 B·9

T01: ~1V! A..OCeH

CALL BURST

Rotate register C through CY:

MOil

R.• C

RAR

MOIl C, fI

Move CY to the SOD enable bit position, A6. Simultaneously set A7 to one, and clear all other bits. Output a tone burst or space, depending on the previous contents of CY:

Mill A, 01H

RAR

RAR

CALL BURST

Clear the accumulator, and output a space:

XRA A

CALL BURST

Keep cycling until the full 9-bit sequence is fin- ished:

B

T01

The BURST subroutine executes the SIM in- struction CYCNO times, at intervals of 29 + 14 (HALFCYC> machine cycles. In between each SIM, bit A7 is complemented. CYCNO should be an even number. If A6 is set upon calling BURST a square-wave will be created. Otherwise, the same code sequence is followed but SOD does not change - thus a spac~ results.

BURST.

11..,.1

(/. ('feNO

(7)

But

SIN

 

<4}

 

t'lVI

E.. HHLFCYC

(7)

BLl2.

()CR

E

(4)

 

JNZ

BtJ2

{7...'10)

 

:<;RI

8€lH

(7)

 

DCR

[j

(4)

 

JNZ

SUi

<7/1e>

 

RET

 

(10)

INPUT ROUTINE

TAPEIN uses a subroutine called BITIN to move the data at the SID pin into the CY. The maximum rate at which SID is read is limited by a delay loop in BITIN.

Initialize the bit counter and the register D, which will keep track of the tone burst time. If a tone

It

\'1

I':·

\'

I...

I,

i

Al-40

Page 180 Page 182
Page 181
Image 181
Intel MCS-80/85 manual But, BLl2, T01 ~1V! A..OCeH, FeNO, BtJ2 €lH
Page 180 Page 182

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.
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