M160 Internet Router Hardware Guide
The PacketForwarding Engine architectureincludes the following components:
Midplane—Transportspackets, notifications, and othersignals between the
FPCs and the PacketForwarding Engine (as well as other system components).
Physical Interface Card (PIC)—Physically connect s the router to fiber-optic
or digital network media. A controller ASIC in each PIC performs control
functions specific tothe PIC media type.
Flexible PIC Concentrator(FPC)—Houses PICs and provides shared memory
for processing incoming andoutgoing packets. Each FPC hosts four I/O
Manager ASICs, which divide incoming data packets into memory blocks (cells)
before passing them to the SFMs, and reassembles cells into data packets when
the packets areready for transmission. The FPC also hosts two Packet Director
ASICs—one distributes incomin g packets among the I/O Manager ASICs, and
the other distributes outgoing packets to the appropriate PICs on the FPC.
Switching and ForwardingModule (SFM)—Hosts an Internet Processor II ASIC,
which makes forwardingdecisions, and two Distributed Buffer Manager ASICs:
one distributes data cells to the shared memory bufferson the FPCs and the
other notifies the FPCs of forwardingdecisions for outgoing packets.
Data Flow through the Packet Forwarding Engine
Use of ASICs promotes efficient movementof data packets through
the system. Packets flow throughthe Packet Forwarding Engine in
the following sequence (see Figure 23):
1. Packets arriveat an incoming PIC interface.
2. The PIC passes the packetsto the FPC, where the Packet DirectorASIC
distributes them among the I/O Manager ASICs.
3. The I/O Manager ASICs process the packet headers, divide the packets into
64-byte data cells, and pass the cells through the midplane to the SFMs.
4. The Distributed Buffer ManagerASICs on the SFMs distribute the data cells
throughout memory buffers located on and shared by all the FPCs.
5. For each packet,an Internet Processor II ASIC on an SFM performs a route
lookup and decides howto forward the packet.
6. The Internet Processor II ASIC notifiesa Distributed Buffer Manager ASIC of
the forwardingdecision, and the Distributed Buffer Manager ASIC forwardsthe
notification to the FPC that hosts the appropriateoutbound interface.
7. The I/O Manager ASIC on the FPC reassembles data cells in shared memory
into data packetsas they are ready for transmission and passes them through
the Packet DirectorASIC to the outbound PIC.
8. The outbound PIC transmits the data packets.
52 Packet ForwardingEngine A rchitecture