4 |
Functional Description
The following diagram illustrates the architecture of the MVME5100 Single Board Computer.
L2 Cache | Bus | |
1M,2M | ||
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| Processor |
| Mezzanine SDRAM | System | |
|
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|
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| 32MB to 512MB | Registers | |
Processor |
|
| MPC604 |
| SDRAM |
| TL16C550 |
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|
| 32MB to 512MB | ||||
MPC7410 |
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|
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|
| UART/9pin |
MPC755 |
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|
| planar |
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|
|
| |
MPC750 |
|
| MHz |
| Hawk Asic |
| FLASH |
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|
|
|
| |||
Clock |
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| System Memory Controller (SMC) | 1MB to 17MB | |||
|
| 100 | and PCI Host Bridge (PHB) |
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| ||
Generator |
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| |
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| RTC/NVRAM/WD |
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| Hawk | M48T37V | |
DEBUG | RJ45 |
|
| ExpansionPCI | |||
| 33MHz |
| |||||
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| ||
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| TL16C550 |
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| |
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| UART |
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|
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| Ethernet 1 | Ethernet 2 | VME Bridge |
|
| 10/100TX10/100TX | RJ45 RJ45 |
| 10/100TX | 10/100TX | Universe 2 | RECEPTACLEIPMC761 |
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|
|
| Buffers | |||
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| |
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| HDR |
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| PMC FrontI/O | Slot2 |
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|
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| PMC Front I/O | SLot1 | Front Panel |
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|
VME P2 | 712/761 or PMC | VME P1 |
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Figure 4-1. MVME5100 Block Diagram
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