D |
Functional Description
A, |
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BA, |
| DQMB0 |
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| SCL A0_SPD CLK1,2 | ||||
WE_L, |
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| CKD |
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RAS_L, |
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CAS_L, |
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Top-side MVME5100-MEZ Connector
| DQMB1 |
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| CLK3,4 |
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| CS_E_L |
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CLK1,2 |
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1 Bank of 9 (x8) |
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SDRAMS |
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| SROM |
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Buffer |
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| SPD |
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LVTH162244 |
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A, | DQMB0 | DQMB1 | DQ, | SCL | A1_SPD | CLK1,2,3,4 |
BA, | CS_C_L | CS_E_L | CKD | SDA |
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WE_L, |
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RAS_L, |
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CAS_L, |
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Note: DQMB1, CS_E_L, A1_SPD,CLK3,4 from Bottom Connector is routed to Top connector
at the DQMB0, CS_C_L and A0_SPD,CLK1,2 pins.
Figure D-1. RAM500 Block Diagram
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