MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
2X Cache Program Operation Flow Diagram
NOTE :
1) DBS must be set before data input.
2) FBA must be an even block.
3) These registers must be set as BSA=1000, BSC=00 and FSA=00.
4) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
.
Start
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA2)
Wait for INT register
Add: F241h DQ=8040h
Last 2Plane PGM?
Map Out
NO
low to high transition
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA3)
Write ‘BSA’, ‘BSC’ of Flash4)
Add: F200h DQ=BSA, BSC
Write 0 to interrupt register5)
Add: F241h DQ=0000h
Write 2X Cache PGM CMD
Add: F220h DQ=007Fh
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA2)
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA3)
Write ‘BSA’, ‘BSC’ of Flash3)
Add: F200h DQ=BSA, BSC
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Write 2X Cache PGM CMD
Add: F220h DQ=007Fh
Wait for INT register
Add: F241h DQ=8040h
low to high transition
DQ[10]=0?
YES
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA2)
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA3)
Write ‘BSA’, ‘BSC’ of Flash3)
Add: F200h DQ=BSA, BSC
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Write 2X PGM CMD
Add: F220h DQ=007Dh
Wait for INT register
Add: F241h DQ=INT
low to high transition
Add: F240h DQ[10]=Error
Read Controller
Status Register
NO
: If program operation results in an error,
map out the block including the page
** DBS, DFS is for DDP
Select DataRAM for DDP1)
Add: F101h DQ=DBS
Write Data into DataRAM0,1
Add: DataRAM DQ=Data(4KB)
Write Data into DataRAM0,1
Add: DataRAM DQ=Data(4KB)
Write Data into DataRAM0,1
Add: DataRAM DQ=Data(4KB)
Read Interrupt register
Add: F241h DQ[6]=WI
DQ[6]=1?
YES
Add: F240h DQ[10]=Error
Read Controller
Status Register
Program completed
DQ[10]=0?
YES
NO
Add: F240h DQ[14]=Lock
Read Controller
Status Register ‘Lock’ bit high
Program Lock Error
NO
NO
in error and copy the target data to another
block.