Samsung KFN4G16Q2A, KFM2G16Q2A Write ’DFS*, FBA’ of Flash Add F100h DQ=DFS, FBA, End, Map out

MuxOneNAND2G(KFM2G16Q2A-DEBx)	FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)

Cache Read Flow Chart

Start

Select DataRAM for DDP3)

Add: F101h DQ=DBS

Write ‘BSA1), BSC2)’ of Flash Add: F200h DQ=BSA, BSC

Write ‘FCBA’ of Flash

Add: F102h DQ=FCBA

Write ‘FCPA, FCSA2)’ of Flash Add: F103h DQ=FCPA, FCSA

Write ’DFS*, FBA’ of Flash

Add: F100h DQ=DFS, FBA

Done with	Yes
(n-1)th command
issue?

No

Write ’DFS*, FBA’ of Flash3) Add: F100h DQ=DFS, FBA

Write ‘FPA, FSA2)’ of Flash3) Add: F107h DQ=FPA, FSA

Wait for INT high State

Add: F241h DQ[15]=INT

Read Controller Status

Register

Add: F240h DQ[10]=Error

Wait for INT high State

Add: F241h DQ[15]=INT

Read Controller Status

Register

Add: F240h DQ[10]=Error

No			DQ[10]=0?
				Yes
	Write 0 to Interrupt register4)
		Add: F241h DQ=0000h

Write ‘FPA, FSA2)’ of Flash

Add: F107h DQ=FPA, FSA

DQ[10]=0?

Yes

No

Write ‘Finish Cache Read

Command’ @ Final Read

Add: F220h DQ=000Ch

Write 0 to Interrupt register4) Add: F241h DQ=0000h

Write ‘Cache Read’ Command

	Add: F220h DQ=000Eh
	Read Controller Status
	Register Add: F240h
DQ[15]=Ongo & DQ[13]=Load
No	DQ[15]=1 & DQ[13]=1 ?
	Yes

*DBS, DFS is for DDP (DFS must be same)

Write 0 to Interrupt register4) Add: F241h DQ=0000h

Write ‘Cache Read’ Command

Add: F220h DQ=000Eh

Host reads data from

DataRAM5)

Host reads data from

DataRAM6)

Wait for INT high State Add: F241h DQ[15]=INT

Read Controller Status

Register

Add: F240h DQ[10]=Error

No

DQ[10]=0?

Yes

Host reads data from

DataRAM

END

Map out

NOTE :

1)In case of first cycle cache read, BSA must be set to 1000 or 1100, and from second cycle cache read, BSA will automatically be switched between DataRAM0 and DataRAM1.

2)BSC, FSA and FCSA must be set to "00".

3)These steps can also be set during INT=High, before next ’Cache Read Command’.

4)’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1

5)When host reads data from DataRAM, host should start from the DataRAM of the first set BSA, and then next DataRAM alternately, as the number of Cache Read.

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