MuxOneNAND2G(KFM2G16Q2A-DEBx)

 

 

 

FLASH MEMORY

 

MuxOneNAND4G(KFN4G16Q2A-DEBx)

 

 

 

5.5 AC Characteristics for Asynchronous Read

 

 

 

 

 

 

 

 

 

 

 

See Timing Diagrams 6.5, 6.6, 6.22 and 6.23.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KFM2G16Q2A/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

KFN4G16Q2A

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

 

Max

 

 

 

 

Access Time from

 

 

Low

 

tCE

-

 

76

ns

 

 

CE

 

 

Asynchronous Access Time from

 

 

 

Low

 

tAA

-

 

76

ns

 

 

AVD

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous Access Time from address valid

 

tACC

-

 

76

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle Time

 

tRC

76

 

-

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low Time

 

tAVDP

12

 

-

ns

 

 

 

AVD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Setup to rising edge of

 

 

 

 

 

 

tAAVDS

5

 

-

ns

 

 

 

AVD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Hold from rising edge of

 

 

 

 

 

tAAVDH

6

 

-

ns

 

 

 

AVD

 

 

Output Enable to Output Valid

 

tOE

-

 

20

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup to

 

 

 

 

 

falling edge

 

tCA

0

 

-

ns

 

 

 

CE

AVD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disable to Output & RDY High Z1)

 

tCEZ

-

 

20

ns

 

 

 

CE

 

 

 

 

 

Disable to Output High Z1)

 

tOEZ

-

 

15

ns

 

 

 

OE

 

 

 

 

 

 

High to

 

 

 

Low

 

tAVDO

0

 

-

ns

 

 

 

AVD

OE

 

 

 

 

Low to RDY Valid

 

tCER

-

 

15

ns

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disable to

 

 

 

 

Enable

 

tWEA

15

 

-

ns

 

 

 

WE

AVD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address to

 

 

 

low

 

tASO2)

10

 

-

ns

 

 

 

OE

NOTE :

1)If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ. If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ. If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.

These parameters are not 100% tested.

2)This Parameter is valid at toggle bit timing in asynchronous read only. (timing diagram 6.21 and 6.22)

5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset

See Timing Diagrams 6.18, 6.19 and 6.20

 

 

Parameter

Symbol

Min

Max

 

 

 

tReady1

-

5

 

RP & Reset Command Latch to BootRAM Access

 

(BootRAM)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tReady2

 

 

 

RP & Reset Command Latch(During Load Routines) to INT High (Note1)

-

10

 

(NAND Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tReady2

 

 

 

RP & Reset Command Latch(During Program Routines) to INT High (Note1)

-

20

 

(NAND Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tReady2

-

500

 

RP & Reset Command Latch(During Erase Routines) to INT High (Note1)

 

(NAND Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tReady2

-

10

 

RP & Reset Command Latch(NOT During Internal Routines) to INT High (Note1)

 

(NAND Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

Pulse Width (Note2)

tRP

200

-

 

RP

 

 

 

 

 

 

Unit

s

s

s

s

s

ns

NOTE :

1)These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.

2)The device may reset if tRP < tRP min(200ns), but this is not guaranteed.

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Image 143
Samsung KFN4G16Q2A, KFM2G16Q2A AC Characteristics for Asynchronous Read, See Timing Diagrams 6.5, 6.6, 6.22, Unit Min Max