MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
3.2 Device Bus Operation
The device bus operations are shown in the table below.
NOTE :
L=VIL (Low), H=VIH (High), X=Don’t Care.
Operation CE OE WE ADQ0~15 RP CLK AV D
Standby H X X High-Z H X X
Warm Reset X X X High-Z L X X
Asynchronous Write L H L Add. In /Data
In HL
Asynchronous Read L L H Add. In /Data
Out HL
Start Initial Burst Read L H H Add. In H
Burst Read L L H Burst Data
Out H
Terminate Burst Read
Cycle HXHHigh-ZHXX
Terminate Burst Read
Cycle via RP XXXHigh-ZLXX
Terminate Current Burst
Read Cycle and Start
New Burst Read Cycle
L H H Add In H
Start Initial Burst Write L H L Add In H
Burst Write L H X Data In H H
Terminate Burst Write
Cycle HHXHigh-ZHXX
Terminate Burst Write
Cycle via RP XXXHigh-ZLXX
Terminate Current Burst
Write Cycle and Start
New Burst Write Cycle
H L Add In H
H