Samsung KFM2G16Q2A Cache Read Operation RM=X, WM=X, Cache-Read flow chart is on the following

MuxOneNAND2G(KFM2G16Q2A-DEBx)		FLASH MEMORY
	MuxOneNAND4G(KFN4G16Q2A-DEBx)
3.8 Cache Read Operation (RM=X, WM=X)

A Normal Load Operation(0000h) consists of sequential operation of ‘sensing from NAND Flash Array to Page Buffer’ and ‘transferring from Page Buffer to DataRAM’.

Cache Read is a method of improving the data read throughput performance of the device by allowing new data to be transferred from the NAND Flash Array memory into a Page Buffer while the previous data that was requested is transferred from the Page Buffer to the DataRAM. This method is called Transfer-While Sensing Operation.

This ability to simultaneously sense a new page shortens the read cycle resulting in performance increase to 108Mbytes/second.

Cache Read Mode is designed to continuously read massive data from random address at a high speed.

The characteristics of Cache read is as follows;

-Before entering ‘First Cache Read Command(000Eh)’, address of two pages which will be read will be set on address registers. The register information follows on next line.

-Register used for first page is Copy-back registers (FCBA, FCPA and FCSA). and the registers used for addressing second page and follow- ing cache read are normal address registers(FBA, FPA and FSA). At Cache Read Operation, FCSA and FSA must be set to "00".

-BSA setting is only required once at ‘First Cache Read’ cycle. From the following cycles, BSA will be automatically switched to select DataRAM0 and DataRAM1 alternately.

-BSC must be fixed as "00"

-To eliminate performance degradation during Ready state(INT high state) due to register setting time, setting registers (FBA, FPA and FSA) during busy state(INT low state) is possible from third address setting onwards.

-Inputting other commands, which is not related to Cache Read, between ‘First Cache Read Command’ and ‘Finish Cache Read Command’ will fail the Cache Read operation.

-In case of performing Cache Read at INT auto mode, INT low setting is not necessary. INT will automatically go to low when Cache Read command is issued.

-If host changes DBS or DFS to access the other chip for DDP while performing cache read operation, it will fail the cache read operation.

Transfer-While Sensing Operation

Host

2) Read

DataRAM

1) Transfer

NAND Flash

Array

Selected Page

Page Buffer

1) Sensing

A Cache-Read flow chart is on the following page.

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