Program Operation | Samsung KFN4G16Q2A, KFM2G16Q2A manual

MuxOneNAND2G(KFM2G16Q2A-DEBx)	FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)

3.11 Program Operation

See Timing Diagram 6.12

The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array.

The device has two 2KB data buffers, each 1 Page (2KB + 64B) in size. Each page has 4 sectors of 512B each main area and 16B spare area. The device can be programmed in units of 1~4 sectors.

The architecture of the DataRAMs permits a simultaneous data-write operation from the Host to one of data buffers and a program operation from the other data buffer to the NAND Flash Array memory. Refer to Section 3.15.2, "Write While Program Operation", for more information.

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited.

Page 63	(64)
	:
Page 31
Page 31	(32)
	:
Page 2
Page 2	(3)
Page 1	(2)
Page 0	(1)

Data register

From the LSB page to MSB page

DATA IN: Data (1) Data (64)

Page 63	(64)
	:
Page 31
Page 31	(1)
	:
Page 2
Page 2	(3)
Page 1	(32)
Page 0	(2)

Data register

Ex.) Random page program (Prohibition)

DATA IN: Data (1) Data (64)

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Image 105

Samsung KFN4G16Q2A, KFM2G16Q2A warranty Program Operation, Addressing for program operation

Contents

KFM2G16Q2A KFN4G16Q2A Revision No History Initial issue Jul Revision No PKG Flash Product Type SelectorNand NOR Architectural Benefits Ordering Information Device Architecture Product FeaturesDevice Performance System Hardware General Overview Error Correction Code Detailed Product DescriptionDefinitions 1 2Gb Product KFM2G16Q2A Pin Configuration 2 4Gb Product KFN4G16Q2A Pin Description Memory Array Organization Block DiagramInternal Nand Array Memory Organization OTP Internal Memory Array Organization Internal Memory Array Information Area Block Sector Internal Nand Array Memory External BufferRAM MemoryExternal BufferRAM Memory Organization Total Size 1KB+32B 2KB+64B BootRAM DataRAM0 DataRAM1 Main area data BootRAMBootRAM DataRAM Block Block Address Sector Size Memory Map Block Block Address 0081h 0000h~00FFh 128KB Block161 0080h 0000h~00FFh 128KB Block1600082h 0000h~00FFh 128KB Block162 0083h 0000h~00FFh 128KB Block163 00E0h 0000h~00FFh 128KB Block193 00C1h Block192 00C0h 0000h~00FFh 128KB00E1h 0000h~00FFh 128KB Block194 00C2h 00E2h 0000h~00FFh 128KB Block195 00C3h 0101h 0000h~00FFh 128KB Block289 0121h 0100h 0000h~00FFh 128KB Block288 0120h0102h 0000h~00FFh 128KB Block290 0122h 0103h 0000h~00FFh 128KB Block291 0123h 0141h 0000h~00FFh 128KB Block353 0161h 0140h 0000h~00FFh 128KB Block352 0160h0142h 0000h~00FFh 128KB Block354 0162h 0143h 0000h~00FFh 128KB Block355 0163h 0000h~00FFh 128KB Block385 0181h Block417 Block384 0180h 0000h~00FFh 128KB Block4160000h~00FFh 128KB Block386 0182h Block418 0000h~00FFh 128KB Block387 0183h Block419 01E0h 0000h~00FFh 128KB 01C0h 0000h~00FFh 128KB01C1h 0000h~00FFh 128KB 01E1h 0000h~00FFh 128KB 0201h 0000h~00FFh 128KB Block545 0221h 0200h 0000h~00FFh 128KB Block544 0220h0202h 0000h~00FFh 128KB Block546 0222h 0203h 0000h~00FFh 128KB Block547 0223h 0241h 0000h~00FFh 128KB Block609 0261h 0240h 0000h~00FFh 128KB Block608 0260h0242h 0000h~00FFh 128KB Block610 0262h 0243h 0000h~00FFh 128KB 0281h 0000h~00FFh 128KB Block673 0280h 0000h~00FFh 128KB Block6720282h 0000h~00FFh 128KB Block674 0283h 0000h~00FFh 128KB Block675 02E0h 0000h~00FFh 128KB Block705 02C1h Block704 02C0h 0000h~00FFh 128KB02E1h 0000h~00FFh 128KB Block706 02C2h 02E2h 0000h~00FFh 128KB Block707 02C3h 0301h 0000h~00FFh 128KB Block801 0321h 0300h 0000h~00FFh 128KB Block800 0320h0302h 0000h~00FFh 128KB Block802 0322h 0303h 0000h~00FFh 128KB Block803 0323h 0341h 0000h~00FFh 128KB Block865 0361h 0340h 0000h~00FFh 128KB Block864 0360h0342h 0000h~00FFh 128KB Block866 0362h 0343h 0000h~00FFh 128KB Block867 0363h 0000h~00FFh 128KB Block897 0381h Block929 Block896 0380h 0000h~00FFh 128KB Block9280000h~00FFh 128KB Block898 0382h Block930 0000h~00FFh 128KB Block899 0383h Block931 03E0h 0000h~00FFh 128KB 03C0h 0000h~00FFh 128KB03C1h 0000h~00FFh 128KB 03E1h 0000h~00FFh 128KB 0401h 0000h~00FFh 128KB Block1057 0421h 0400h 0000h~00FFh 128KB Block1056 0420h0402h 0000h~00FFh 128KB Block1058 0422h 0403h 0000h~00FFh 128KB Block1059 0423h 0460h 0000h~00FFh 128KB 0440h 0000h~00FFh 128KB0441h 0000h~00FFh 128KB 0461h 0000h~00FFh 128KB 0481h 0000h~00FFh 128KB 0480h 0000h~00FFh 128KB0482h 0000h~00FFh 128KB 0483h 0000h~00FFh 128KB 04C1h 0000h~00FFh 128KB Block1249 04E1h 04C0h 0000h~00FFh 128KB Block1248 04E0h04C2h 0000h~00FFh 128KB Block1250 04E2h 04C3h 0000h~00FFh 128KB Block1251 04E3h 0501h 0000h~00FFh 128KB Block1313 0521h 0500h 0000h~00FFh 128KB Block1312 0520h0502h 0000h~00FFh 128KB Block1314 0522h 0503h 0000h~00FFh 128KB Block1315 0523h 0541h 0000h~00FFh 128KB Block1377 0561h 0540h 0000h~00FFh 128KB Block1376 0560h0542h 0000h~00FFh 128KB Block1378 0562h 0543h 0000h~00FFh 128KB Block1379 0563h 0581h 0000h~00FFh 128KB Block1441 0580h 0000h~00FFh 128KB Block14400582h 0000h~00FFh 128KB Block1442 0583h 0000h~00FFh 128KB Block1443 05C1h 0000h~00FFh 128KB Block1505 05E1h 05C0h 0000h~00FFh 128KB Block1504 05E0h05C2h 0000h~00FFh 128KB Block1506 05E2h 05C3h 0000h~00FFh 128KB Block1507 05E3h 0601h 0000h~00FFh 128KB Block1569 0621h 0600h 0000h~00FFh 128KB Block1568 0620h0602h 0000h~00FFh 128KB Block1570 0622h 0603h 0000h~00FFh 128KB Block1571 0623h 0641h 0000h~00FFh 128KB Block1633 0661h 0640h 0000h~00FFh 128KB Block1632 0660h0642h 0000h~00FFh 128KB Block1634 0662h 0643h 0000h~00FFh 128KB Block1635 0663h 0681h 0000h~00FFh 128KB Block1697 0680h 0000h~00FFh 128KB Block16960682h 0000h~00FFh 128KB Block1698 0683h 0000h~00FFh 128KB Block1699 06C1h 0000h~00FFh 128KB Block1761 06E1h 06C0h 0000h~00FFh 128KB Block1760 06E0h06C2h 0000h~00FFh 128KB Block1762 06E2h 06C3h 0000h~00FFh 128KB Block1763 06E3h 0701h 0000h~00FFh 128KB Block1825 0721h 0700h 0000h~00FFh 128KB Block1824 0720h0702h 0000h~00FFh 128KB Block1826 0722h 0703h 0000h~00FFh 128KB Block1827 0723h 0741h 0000h~00FFh 128KB Block1889 0761h 0740h 0000h~00FFh 128KB Block1888 0760h0742h 0000h~00FFh 128KB Block1890 0762h 0743h 0000h~00FFh 128KB Block1891 0763h 0000h~00FFh 128KB Block1921 0781h Block1953 Block1920 0780h 0000h~00FFh 128KB Block19520000h~00FFh 128KB Block1922 0782h Block1954 0000h~00FFh 128KB Block1923 0783h Block1955 07C1h 0000h~00FFh 128KB Block2017 07E1h 07C0h 0000h~00FFh 128KB Block2016 07E0h07C2h 0000h~00FFh 128KB Block2018 07E2h 07C3h 0000h~00FFh 128KB Block2019 07E3h Word Byte Lnternal Memory Spare Area Assignment Division Address Size Usage Description External Memory BufferRAM Address Map External Memory Map Detail Information 0800h~08FFh512B 0900h~09FFh512B DataM8048h~804Fh16B Buf External Memory Spare Area Assignment ECC Code for Main area data 3rd 8026h 1004Ch Managed by Internal ECC logic DataS 8023h 10046h8027h 1004Eh 8028h 10050h 8029h 10052h Managed by Internal ECC logic 8048h Buf Word Byte8049h Managed by Internal ECC logic Registers Register Address MapAddress Name Host Description Manufacturer ID Register F000h R Device ID Register F001h R Device ID DefaultDevice Identification Description DeviceID150 Version ID Register F002h F003h, default = 0800h DataBufSizeData Buffer Size Register F003h R This Register is reserved for internal use Boot Buffer Size Register F004h R Number of Buffers Register F005h RTechnology Register F006h R Start Address2 Register F101h R/W Start Address1 Register F100h R/W Start Address4 Register F103h R/W Start Address3 Register F102h R/WFcba Fcpa FCSA1 Start Address6 Register F105h Start Address5 Register F104h R/WStart Address7 Register F106h Start Address8 Register F107h R/W Start Buffer Register F200h R/W BSABSC Acceptable Command Register F220h R/WCMD Operation Two Methods to Clear Interrupt Register in Command Input Write command into INT will automaticallyInterrupt Register Brwl System Configuration 1 Register F221h R, R/W Burst Length BL Information119 Definition Description Burst Length BLRDY Polarity RDYpol Information7 INT Polarity INTpol Information6 Iobe Write Mode Information1 Definition Write Mode WMMRSMode register Setting Description Mode Description Bwps Controller Status Register F240h R System Configuration 2 Register F222h Error = ready defaultError Information10 Sector/Page Load/Program/CopyBack Program Rstb OtplOtpbl Plane2 Previous Plane1 CurrentPlane2 Current Time Out to Controller Status Register Output Modes Flash Memory Interrupt Status Register F241h R/W INTRsti EI Interrupt Status Conditions Default State Valid Default State ValidReset Interrupt Rsti Rsti Interrupt Status Conditions Default State Valid End Block Address Register F24Dh Start Block Address Register F24Ch R/WNand Flash Write Protection Status Register F24Eh R SBA ECC Status Register FF00h R Error Status ERm, ERs ECC StatusERm3 ERs3 ERm2 ERs2 ERm1 ERs1 ERm0 ERs01 ECC Information150 Reserved0000000000 ECClogSector0 ECCposIO0 Reserved0000 ECCposWord0 ECCposIO0Reserved0000 ECCposWord1 ECCposIO1 Reserved0000000000 ECClogSector1 ECCposIO1 Reserved0000000000 ECClogSector2 ECCposIO2 Reserved0000 ECCposWord2 ECCposIO2Reserved0000 ECCposWord3 ECCposIO3 Reserved0000000000 ECClogSector3 ECCposIO3 ECC Log Sector ECClogSector Information Error Position Command Based Operation Reset MuxOneNAND Add BP1 Data 00F0hAdd Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Load MuxOneNAND Command Reset MuxOneNAND CommandRead Identification Data Command Identification Data Description Address Data Out Device Bus Operation Operation ADQ0~15CLK AVD Reset Mode Operation Warm Reset Mode Operation Cold Reset Mode OperationHot Reset Mode Operation Nand Flash Core Reset Mode Operation Write Protection Operation BootRAM Write Protection OperationNand Flash Array Write Protection Operation Nand Array Write Protection States Unlocked All Block Unlock Command Sequence Unlocked Unlock Command SequenceLocked Lock Command Sequence Unlocked Nand Array Write Protection State Locked-tight Lock-Tight Command Sequence Nand Flash Array Write Protection State DiagramPower On Locked-tight Nand Array Write Protection State Add F101h DQ=DBS Data Protection Operation Flow DiagramAdd F100h DQ=DFS Add F24Ch DQ=SBA Add F241h DQ=0000h All Block Unlock Flow DiagramDQ=0027h Add F241h DQ15=INT Load Operation Data Protection During Power Down OperationYES Host reads data from DataRAM Read completed Asynchronous Read Mode Operation RM=0, WM=0 Synchronous Read Mode Operation RM=1, WM=XRead Operation 2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation Continuous Linear Burst Read Operation Output Disable Mode Operation Programmable Burst Read Latency OperationHandshaking Operation Cache Read Operation RM=X, WM=X Cache-Read flow chart is on the following Write ’DFS*, FBA’ of Flash Add F100h DQ=DFS, FBA Write ‘Cache Read’ Command Add F220h DQ=000EhEND Map out 4th Status Command Host reads 1st 1st DQ0 Address A/DQ15 Setting INT 2ndCache Read Diagram Setting Read Read data from DataRAM Cont Synchronous Burst Block Read OperationRM=1, WM=X See Timing Diagram 6.3 Terminating Synchronous Burst Block Read Synchronous Burst Block Read Boundary 102 Four Clock Burst Read Latency default condition 103 Synchronous Burst Block Read Operation Flow Chart Synchronous WriteRM=1, WM=1 See Timing Diagram 6.8, 6.9 Addressing for program operation Program Operation Program Lock Error Program Error Program Operation Flow DiagramADD DP DQ=Data-in Add F100h DQ=DFS*’, FBA 107 11.1 2X Program Operation Add F100h DQ=DFS*, FBA 2X Program Operation Flow DiagramAdd F220h DQ=007Dh 108 109 11.2 2X Cache Program Operation 110 DBS, DFS is for DDP 111 11.3 2X Interleave Cache Program Operation Last 2 Plane PGM For a chip? 2X Interleave Cache Program Operation Flow Diagram StartFor a chip 112 113 Copy-Back Program Operation Flash Memory 115 Copy-Back Program Operation with Random Data Input Block Erase Operation Erase Operation Locked Blocks Multi-Block Erase Operation Multi-Block Erase Verify Read Operation Multi Block Erase/ Multi Block Erase Verify Read Flow ChartAdd F220h DQ=0095h Add F240h DQ10=0 Erase Suspend / Erase Resume Operation Erase Suspend During a Block Erase Operation119 OTP Operation 1st Block OTP Area Structure OTP Block Area Structure 122 OTP Block Load Operation Programming the OTP Area OTP Block Program Operation OTP Block Program Operation Flow Chart Write ‘DFS, FBA’ of Flash Add F100h DQ=DFS, FBA3OTPL=0? YES OTP Block Lock Operation Locking the OTPOTP Lock Operation Steps Automatically Updated Add F241h DQ15=INT Do Cold resetWrite ’DFS, FBA’ of Flash Add F100h DQ=DFS, FBA3 126 14.4 1st Block OTP Lock Operation Locking the 1st Block OTP1st Block OTP Lock Operation Steps 128 OTP and 1st Block OTP Lock Operation Locking the OTP and 1st Block OTPOTP and 1st Block OTP simultaneous Lock Operation Steps 130 Read-While-Load Operation Dual OperationsWrite-While-Program Operation Data Load DB0 ADQDB1 AVD INT 133 Status DQ15~DQ7 16 DQ6 Toggle BitDQ6 DQ5~DQ0 Progress Data Loading Don’t Care ECC Bypass Operation ECC Operation Invalid Block Identification Table Operation Invalid Block Operation Invalid Block Table Creation Flow Chart Start Invalid Block Replacement Operation Block Replacement Operation Sequence 1st 1th NthBlock B Absolute Maximum Ratings Operating ConditionsKFM2G16Q2A Test Conditions DC Characteristics AC Test Conditions Valid Block CharacteristicsDevice Capacitance DDP AC Characteristics for Synchronous Burst Read 66MHz 83MHz UnitMax Min See Timing Diagrams 6.5, 6.6, 6.22 AC Characteristics for Asynchronous ReadSee Timing Diagrams 6.18, 6.19 Parameter Symbol Min Max KFN4G16Q2A AC Characteristics for Burst Write Operation AC Characteristics for Asynchronous WriteMin Max 66MHz 83MHz Unit Min AC Characteristics for Load/Program/Erase Performance AC Characteristics for INT Auto ModeAC Characteristics for Synchronous Burst Block Read Continuous Linear Burst Read Mode with Wrap Around 8-Word Linear Burst Read Mode with Wrap AroundCLK RDY 147 148 Synchronous Burst Block Read Timing Burst block read 149 Asynchronous Read VA Transition Before See AC Characteristics Table DQ0 DQ15Low Asynchronous Read VA Transition After AVD Low Valid WD Asynchronous WriteHi-Z 151 Burst Write Operation followed by Burst Read 8-Word Linear Burst Write Mode≈D7 152 153 Start Initial Burst Write Operation Load Command Sequence last two cycles Read Data See AC Characteristics Tables 5.5, 5.7Load Operation Timing Bit 155 Program Operation Timing 13 2X Program Operation Timing Ongoing StatusADQ0~ADQ15 . . A1 14 2X Cache Program Operation TimingMuxOneNAND2GKFM2G16Q2A MuxOneNAND4GKFN4G16Q2A Cache Program 15 2X InterleaveADQ0~ ADQ15 Erase Command Sequence Read Status Data Block Erase Operation Timing159 Bootcode copy done Cold Reset TimingBootcode copy Default See AC Characteristics Tables Warm Reset TimingCE, OE INT bit ADQi Hot Reset TimingBPNote 00F0h Or F220h Or 00F3h Idle Nand Flash Core Reset Timing Data Protection Timing During Power Down163 Status RD Hi-Z RDY164 INT auto mode Write command into Command Register INT will automatically165 Methods of Determining Interrupt Status INT Type Mono INT Type DDP166 Synchronous Mode Using the INT Pin Asynchronous Mode Using the INT PinINT Pin to a Host General Purpose I/O Handshaking Mode Non-Handshaking Mode Polling the Interrupt Register Status Bit168 INT pol = ‘High’ Default Determining Rp Value DDP, QDP onlyRpohm Vcc or Vccq INT pol = ‘Low’~50k ohm Ready Vss KFN4G16Q2A @ Vcc = 1.8V, Ta = 25C , CL = 30pF Boot Loaders in MuxOneNAND Boot SequenceBoot Sequence Boot Loaders in MuxOneNAND Description BL2 NBL3 NBL1 NBL2BL1 BL1 BL2 2G product KFM2G16Q2A 4G product KFN4G16Q2A173