Adq, DB0, DB1, Avd Int | Samsung KFM2G16Q2A, KFN4G16Q2A specification

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Read While Load Diagram

Page A

Page B

Data Load

ADQ

Add_ Flash Add_

DB0

Int_

0000h

CMD_

LD_

Data Load

CS_ Read Add_

Flash

Add_

DB1

Int_

0000h

CMD_

LD_

_DB1

0~15

reg _add

reg

_add

reg

CMD

_DB0

reg Status reg

_add

reg

_add

reg

CMD

Data Read 2)

_DB0 *

AVD

INT

Int_reg : Interrupt Register Address

Add_reg : Address Register Address

Flash_add : Flash Address to be loaded

DBn_add : DataRAM Address to be loaded

CMD_reg : Command Register Address

LD_CMD : Load Command

Data Load_DBn : Load Data from NAND Flash Array to DataRAMn

CS_reg : Controller Status Register Address

Data Read_DBn : Read Data from DBn

MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx)

FLASH MEMORY

Page 132

Image 132

Samsung KFM2G16Q2A, KFN4G16Q2A warranty Adq, DB0, DB1, Avd Int

Contents

KFM2G16Q2A KFN4G16Q2A Initial issue Jul Revision No History Revision No Flash Product Type Selector PKGNand NOR Ordering Information Architectural Benefits Product Features Device ArchitectureDevice Performance System Hardware General Overview Error Correction Code Detailed Product DescriptionDefinitions Pin Configuration 1 2Gb Product KFM2G16Q2A 2 4Gb Product KFN4G16Q2A Pin Description Block Diagram Memory Array OrganizationInternal Nand Array Memory Organization OTP Internal Memory Array Information Area Block Sector Internal Memory Array Organization External BufferRAM Memory Internal Nand Array MemoryExternal BufferRAM Memory Organization Total Size 1KB+32B 2KB+64B BootRAM DataRAM0 DataRAM1 Main area data BootRAMBootRAM DataRAM Memory Map Block Block Address Sector Size Block Block Address 0080h 0000h~00FFh 128KB Block160 0081h 0000h~00FFh 128KB Block1610082h 0000h~00FFh 128KB Block162 0083h 0000h~00FFh 128KB Block163 Block192 00C0h 0000h~00FFh 128KB 00E0h 0000h~00FFh 128KB Block193 00C1h00E1h 0000h~00FFh 128KB Block194 00C2h 00E2h 0000h~00FFh 128KB Block195 00C3h 0100h 0000h~00FFh 128KB Block288 0120h 0101h 0000h~00FFh 128KB Block289 0121h0102h 0000h~00FFh 128KB Block290 0122h 0103h 0000h~00FFh 128KB Block291 0123h 0140h 0000h~00FFh 128KB Block352 0160h 0141h 0000h~00FFh 128KB Block353 0161h0142h 0000h~00FFh 128KB Block354 0162h 0143h 0000h~00FFh 128KB Block355 0163h Block384 0180h 0000h~00FFh 128KB Block416 0000h~00FFh 128KB Block385 0181h Block4170000h~00FFh 128KB Block386 0182h Block418 0000h~00FFh 128KB Block387 0183h Block419 01C0h 0000h~00FFh 128KB 01E0h 0000h~00FFh 128KB01C1h 0000h~00FFh 128KB 01E1h 0000h~00FFh 128KB 0200h 0000h~00FFh 128KB Block544 0220h 0201h 0000h~00FFh 128KB Block545 0221h0202h 0000h~00FFh 128KB Block546 0222h 0203h 0000h~00FFh 128KB Block547 0223h 0240h 0000h~00FFh 128KB Block608 0260h 0241h 0000h~00FFh 128KB Block609 0261h0242h 0000h~00FFh 128KB Block610 0262h 0243h 0000h~00FFh 128KB 0280h 0000h~00FFh 128KB Block672 0281h 0000h~00FFh 128KB Block6730282h 0000h~00FFh 128KB Block674 0283h 0000h~00FFh 128KB Block675 Block704 02C0h 0000h~00FFh 128KB 02E0h 0000h~00FFh 128KB Block705 02C1h02E1h 0000h~00FFh 128KB Block706 02C2h 02E2h 0000h~00FFh 128KB Block707 02C3h 0300h 0000h~00FFh 128KB Block800 0320h 0301h 0000h~00FFh 128KB Block801 0321h0302h 0000h~00FFh 128KB Block802 0322h 0303h 0000h~00FFh 128KB Block803 0323h 0340h 0000h~00FFh 128KB Block864 0360h 0341h 0000h~00FFh 128KB Block865 0361h0342h 0000h~00FFh 128KB Block866 0362h 0343h 0000h~00FFh 128KB Block867 0363h Block896 0380h 0000h~00FFh 128KB Block928 0000h~00FFh 128KB Block897 0381h Block9290000h~00FFh 128KB Block898 0382h Block930 0000h~00FFh 128KB Block899 0383h Block931 03C0h 0000h~00FFh 128KB 03E0h 0000h~00FFh 128KB03C1h 0000h~00FFh 128KB 03E1h 0000h~00FFh 128KB 0400h 0000h~00FFh 128KB Block1056 0420h 0401h 0000h~00FFh 128KB Block1057 0421h0402h 0000h~00FFh 128KB Block1058 0422h 0403h 0000h~00FFh 128KB Block1059 0423h 0440h 0000h~00FFh 128KB 0460h 0000h~00FFh 128KB0441h 0000h~00FFh 128KB 0461h 0000h~00FFh 128KB 0480h 0000h~00FFh 128KB 0481h 0000h~00FFh 128KB0482h 0000h~00FFh 128KB 0483h 0000h~00FFh 128KB 04C0h 0000h~00FFh 128KB Block1248 04E0h 04C1h 0000h~00FFh 128KB Block1249 04E1h04C2h 0000h~00FFh 128KB Block1250 04E2h 04C3h 0000h~00FFh 128KB Block1251 04E3h 0500h 0000h~00FFh 128KB Block1312 0520h 0501h 0000h~00FFh 128KB Block1313 0521h0502h 0000h~00FFh 128KB Block1314 0522h 0503h 0000h~00FFh 128KB Block1315 0523h 0540h 0000h~00FFh 128KB Block1376 0560h 0541h 0000h~00FFh 128KB Block1377 0561h0542h 0000h~00FFh 128KB Block1378 0562h 0543h 0000h~00FFh 128KB Block1379 0563h 0580h 0000h~00FFh 128KB Block1440 0581h 0000h~00FFh 128KB Block14410582h 0000h~00FFh 128KB Block1442 0583h 0000h~00FFh 128KB Block1443 05C0h 0000h~00FFh 128KB Block1504 05E0h 05C1h 0000h~00FFh 128KB Block1505 05E1h05C2h 0000h~00FFh 128KB Block1506 05E2h 05C3h 0000h~00FFh 128KB Block1507 05E3h 0600h 0000h~00FFh 128KB Block1568 0620h 0601h 0000h~00FFh 128KB Block1569 0621h0602h 0000h~00FFh 128KB Block1570 0622h 0603h 0000h~00FFh 128KB Block1571 0623h 0640h 0000h~00FFh 128KB Block1632 0660h 0641h 0000h~00FFh 128KB Block1633 0661h0642h 0000h~00FFh 128KB Block1634 0662h 0643h 0000h~00FFh 128KB Block1635 0663h 0680h 0000h~00FFh 128KB Block1696 0681h 0000h~00FFh 128KB Block16970682h 0000h~00FFh 128KB Block1698 0683h 0000h~00FFh 128KB Block1699 06C0h 0000h~00FFh 128KB Block1760 06E0h 06C1h 0000h~00FFh 128KB Block1761 06E1h06C2h 0000h~00FFh 128KB Block1762 06E2h 06C3h 0000h~00FFh 128KB Block1763 06E3h 0700h 0000h~00FFh 128KB Block1824 0720h 0701h 0000h~00FFh 128KB Block1825 0721h0702h 0000h~00FFh 128KB Block1826 0722h 0703h 0000h~00FFh 128KB Block1827 0723h 0740h 0000h~00FFh 128KB Block1888 0760h 0741h 0000h~00FFh 128KB Block1889 0761h0742h 0000h~00FFh 128KB Block1890 0762h 0743h 0000h~00FFh 128KB Block1891 0763h Block1920 0780h 0000h~00FFh 128KB Block1952 0000h~00FFh 128KB Block1921 0781h Block19530000h~00FFh 128KB Block1922 0782h Block1954 0000h~00FFh 128KB Block1923 0783h Block1955 07C0h 0000h~00FFh 128KB Block2016 07E0h 07C1h 0000h~00FFh 128KB Block2017 07E1h07C2h 0000h~00FFh 128KB Block2018 07E2h 07C3h 0000h~00FFh 128KB Block2019 07E3h Lnternal Memory Spare Area Assignment Word Byte External Memory BufferRAM Address Map Division Address Size Usage Description External Memory Map Detail Information 0800h~08FFh512B 0900h~09FFh512B DataM8048h~804Fh16B External Memory Spare Area Assignment Buf Managed by Internal ECC logic DataS 8023h 10046h ECC Code for Main area data 3rd 8026h 1004Ch8027h 1004Eh 8028h 10050h 8029h 10052h Managed by Internal ECC logic Buf Word Byte 8048h8049h Managed by Internal ECC logic Registers Register Address MapAddress Name Host Description Manufacturer ID Register F000h R Device ID Default Device ID Register F001h RDevice Identification Description DeviceID150 F003h, default = 0800h DataBufSize Version ID Register F002hData Buffer Size Register F003h R This Register is reserved for internal use Boot Buffer Size Register F004h R Number of Buffers Register F005h RTechnology Register F006h R Start Address1 Register F100h R/W Start Address2 Register F101h R/W Start Address3 Register F102h R/W Start Address4 Register F103h R/WFcba Fcpa FCSA1 Start Address5 Register F104h R/W Start Address6 Register F105hStart Address7 Register F106h Start Address8 Register F107h R/W Start Buffer Register F200h R/W BSABSC Command Register F220h R/W AcceptableCMD Operation Two Methods to Clear Interrupt Register in Command Input Write command into INT will automaticallyInterrupt Register System Configuration 1 Register F221h R, R/W Brwl Burst Length BL Burst Length BL Information119 Definition DescriptionRDY Polarity RDYpol Information7 INT Polarity INTpol Information6 Iobe Write Mode WM Write Mode Information1 DefinitionMRSMode register Setting Description Mode Description Bwps System Configuration 2 Register F222h Controller Status Register F240h R = ready default ErrorError Information10 Sector/Page Load/Program/CopyBack Program Rstb OtplOtpbl Plane1 Current Plane2 PreviousPlane2 Current Time Out to Controller Status Register Output Modes Flash Memory Interrupt Status Register F241h R/W INTRsti Default State Valid EI Interrupt Status Conditions Default State ValidReset Interrupt Rsti Rsti Interrupt Status Conditions Default State Valid Start Block Address Register F24Ch R/W End Block Address Register F24DhNand Flash Write Protection Status Register F24Eh R SBA Error Status ERm, ERs ECC Status ECC Status Register FF00h RERm3 ERs3 ERm2 ERs2 ERm1 ERs1 ERm0 ERs01 ECC Information150 Reserved0000 ECCposWord0 ECCposIO0 Reserved0000000000 ECClogSector0 ECCposIO0Reserved0000 ECCposWord1 ECCposIO1 Reserved0000000000 ECClogSector1 ECCposIO1 Reserved0000 ECCposWord2 ECCposIO2 Reserved0000000000 ECClogSector2 ECCposIO2Reserved0000 ECCposWord3 ECCposIO3 Reserved0000000000 ECClogSector3 ECCposIO3 ECClogSector Information Error Position ECC Log Sector Command Based Operation Reset MuxOneNAND Add BP1 Data 00F0hAdd Data 00E0h 0000h3 Read Identification Data XXXXh4 0090h Reset MuxOneNAND Command Load MuxOneNAND CommandRead Identification Data Command Identification Data Description Address Data Out Device Bus Operation Operation ADQ0~15CLK AVD Reset Mode Operation Cold Reset Mode Operation Warm Reset Mode OperationHot Reset Mode Operation Nand Flash Core Reset Mode Operation BootRAM Write Protection Operation Write Protection OperationNand Flash Array Write Protection Operation Nand Array Write Protection States Unlocked Unlock Command Sequence Unlocked All Block Unlock Command SequenceLocked Lock Command Sequence Unlocked Nand Array Write Protection State Nand Flash Array Write Protection State Diagram Locked-tight Lock-Tight Command SequencePower On Locked-tight Nand Array Write Protection State Data Protection Operation Flow Diagram Add F101h DQ=DBSAdd F100h DQ=DFS Add F24Ch DQ=SBA All Block Unlock Flow Diagram Add F241h DQ=0000hDQ=0027h Add F241h DQ15=INT Data Protection During Power Down Operation Load OperationYES Host reads data from DataRAM Read completed Asynchronous Read Mode Operation RM=0, WM=0 Synchronous Read Mode Operation RM=1, WM=XRead Operation Continuous Linear Burst Read Operation 2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation Output Disable Mode Operation Programmable Burst Read Latency OperationHandshaking Operation Cache-Read flow chart is on the following Cache Read Operation RM=X, WM=X Write ‘Cache Read’ Command Add F220h DQ=000Eh Write ’DFS*, FBA’ of Flash Add F100h DQ=DFS, FBAEND Map out 1st DQ0 Address A/DQ15 Setting INT 2nd 4th Status Command Host reads 1stCache Read Diagram Setting Read Read data from DataRAM Cont See Timing Diagram 6.3 Synchronous Burst Block Read OperationRM=1, WM=X Terminating Synchronous Burst Block Read Synchronous Burst Block Read Boundary Four Clock Burst Read Latency default condition 102 Synchronous Burst Block Read Operation Flow Chart 103 See Timing Diagram 6.8, 6.9 Synchronous WriteRM=1, WM=1 Program Operation Addressing for program operation Program Operation Flow Diagram Program Lock Error Program ErrorADD DP DQ=Data-in Add F100h DQ=DFS*’, FBA 11.1 2X Program Operation 107 2X Program Operation Flow Diagram Add F100h DQ=DFS*, FBAAdd F220h DQ=007Dh 108 11.2 2X Cache Program Operation 109 DBS, DFS is for DDP 110 11.3 2X Interleave Cache Program Operation 111 2X Interleave Cache Program Operation Flow Diagram Start Last 2 Plane PGM For a chip?For a chip 112 Copy-Back Program Operation 113 Flash Memory Copy-Back Program Operation with Random Data Input 115 Erase Operation Block Erase Operation Multi-Block Erase Operation Locked Blocks Multi Block Erase/ Multi Block Erase Verify Read Flow Chart Multi-Block Erase Verify Read OperationAdd F220h DQ=0095h Add F240h DQ10=0 Erase Suspend / Erase Resume Operation Erase Suspend During a Block Erase Operation119 OTP Operation OTP Block Area Structure 1st Block OTP Area Structure OTP Block Load Operation 122 OTP Block Program Operation Programming the OTP Area OTP Block Program Operation Flow Chart Write ‘DFS, FBA’ of Flash Add F100h DQ=DFS, FBA3OTPL=0? YES OTP Block Lock Operation Locking the OTPOTP Lock Operation Steps Add F241h DQ15=INT Do Cold reset Automatically UpdatedWrite ’DFS, FBA’ of Flash Add F100h DQ=DFS, FBA3 126 14.4 1st Block OTP Lock Operation Locking the 1st Block OTP1st Block OTP Lock Operation Steps 128 OTP and 1st Block OTP Lock Operation Locking the OTP and 1st Block OTPOTP and 1st Block OTP simultaneous Lock Operation Steps 130 Dual Operations Read-While-Load OperationWrite-While-Program Operation Data Load ADQ DB0DB1 AVD INT 133 16 DQ6 Toggle Bit Status DQ15~DQ7DQ6 DQ5~DQ0 Progress Data Loading Don’t Care ECC Operation ECC Bypass Operation Invalid Block Operation Invalid Block Identification Table Operation Invalid Block Replacement Operation Invalid Block Table Creation Flow Chart Start Block Replacement Operation Sequence 1st 1th NthBlock B Absolute Maximum Ratings Operating ConditionsKFM2G16Q2A DC Characteristics Test Conditions Valid Block Characteristics AC Test ConditionsDevice Capacitance DDP AC Characteristics for Synchronous Burst Read 66MHz 83MHz UnitMax Min AC Characteristics for Asynchronous Read See Timing Diagrams 6.5, 6.6, 6.22See Timing Diagrams 6.18, 6.19 Parameter Symbol Min Max KFN4G16Q2A AC Characteristics for Asynchronous Write AC Characteristics for Burst Write OperationMin Max 66MHz 83MHz Unit Min AC Characteristics for Load/Program/Erase Performance AC Characteristics for INT Auto ModeAC Characteristics for Synchronous Burst Block Read 8-Word Linear Burst Read Mode with Wrap Around Continuous Linear Burst Read Mode with Wrap AroundCLK RDY 147 Synchronous Burst Block Read Timing 148 149 Burst block read See AC Characteristics Table DQ0 DQ15 Asynchronous Read VA Transition BeforeLow Asynchronous Read VA Transition After AVD Low Asynchronous Write Valid WDHi-Z 151 8-Word Linear Burst Write Mode Burst Write Operation followed by Burst Read≈D7 152 Start Initial Burst Write Operation 153 See AC Characteristics Tables 5.5, 5.7 Load Command Sequence last two cycles Read DataLoad Operation Timing Bit Program Operation Timing 155 13 2X Program Operation Timing Ongoing StatusADQ0~ADQ15 . . A1 14 2X Cache Program Operation TimingMuxOneNAND2GKFM2G16Q2A MuxOneNAND4GKFN4G16Q2A 15 2X Interleave Cache ProgramADQ0~ ADQ15 Erase Command Sequence Read Status Data Block Erase Operation Timing159 Cold Reset Timing Bootcode copy doneBootcode copy Default Warm Reset Timing See AC Characteristics TablesCE, OE INT bit Hot Reset Timing ADQiBPNote 00F0h Or F220h Or 00F3h Idle Nand Flash Core Reset Timing Data Protection Timing During Power Down163 Status RD Hi-Z RDY164 INT auto mode Write command into Command Register INT will automatically165 Methods of Determining Interrupt Status INT Type Mono INT Type DDP166 Synchronous Mode Using the INT Pin Asynchronous Mode Using the INT PinINT Pin to a Host General Purpose I/O Handshaking Mode Non-Handshaking Mode Polling the Interrupt Register Status Bit168 INT pol = ‘High’ Default Determining Rp Value DDP, QDP onlyRpohm INT pol = ‘Low’ Vcc or Vccq~50k ohm Ready Vss KFN4G16Q2A @ Vcc = 1.8V, Ta = 25C , CL = 30pF Boot Sequence Boot Loaders in MuxOneNANDBoot Sequence Boot Loaders in MuxOneNAND Description NBL3 NBL1 NBL2 BL2BL1 BL1 BL2 2G product KFM2G16Q2A 4G product KFN4G16Q2A173