Samsung KFN4G16Q2A Synchronous Burst Block Read OperationRM=1, WM=X, See Timing Diagram 6.3

MuxOneNAND2G(KFM2G16Q2A-DEBx)	FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)

3.9 Synchronous Burst Block Read Operation(RM=1, WM=X)

See Timing Diagram 6.3 and 6.4.

MuxOneNAND is internally composed of two DataRAMs and NAND Flash Array. And for host to read data from NAND Cell Array, load operation which moves data from NAND Cell Array to DataRAM is required. After this load operation, host may use various read mode, such as synchronous burst read or asynchronous read, to read data from MuxOneNAND.

But these types of read mode require issuing of address and Load Command for each page, and CPU had the burden of calculating address to be read. To solve this burden, Synchronous Burst Block Read Mode is introduced, which enables host to read the data of succeeding page with CLK toggle, after initial address setting and command input. This Synchronous Burst Block Read is intended to transfer continuous mas- sive data in NAND Flash Array at high speed, and it sequentially reads out data only from Main Area, where large sized data is stored.

The addresses set for Synchronous Burst Block Read is Start Page Address(FPA), Number of Page(FPC) and BSA. Note that the number of page set by FPC should not exceed the block boundary, since page wrap-around is not supported. And from the start page address to desired number of page, Synchronous Burst Block Read will output data by CLK toggle and CE enable/disable. FPC must be set from 3pages to 64pages. (Refer to 2.8.13)

The Host can access MuxOneNAND during Synchronous Burst Block Read in between every 1-page of read cycle. When host accesses Dat- aRAMs, the start address of DataRAMs must be a multiple of 4. In doing this, INT pin or bit is used as indicator signal. Thus, before host reads 1-page data from DataRAM, host must confirm INT pin or bit return low to high, and then enable CE to read 1-page of data. And when host read operation for this 1-page is done, INT will automatically turn low. Note that INT auto mode is a mandatory option for Synchronous Burst Block Read, and WE must always be set high throughout this operation.

Therefore, the steps are as follows;

1.Host will deassert CE of MuxOneNAND after checking the indicator(INT pin / bit) turn low.

2.And then assert the CE of other device to perform another operation.

3.Then disable this other device by deasserting CE when desired operation is done.

4.Once the host confirms the INT pin or bit of MuxOneNAND turn low to high, host may read the data of following page by asserting CE(refer to synchronous burst block read operation timing).

Return of INT pin to high implies the internal load operation from NAND Flash Array to DataRAM is complete. Also, even when the host is NOT accessing other device, this assert/deassert of CE step is necessary.

To read data from this loaded 1 page, same 4, 8, 16, 32, continuous (1K word) linear burst read operation of synchronous burst read may be utilized.

In conclusion, by supporting indicator signal such as INT pin or bit, host may access other device without terminating continuous linear syn- chronous burst block read, while using continuous linear burst read mode as synchronous block read within 1 block between every (n) page and (n+1) page. (refer to synchronous burst block read boundary)

For 1 bit error during Synchronous Burst Block Read, ECC correction will be done automatically, and Controller Status Register(F240h) will show ‘load ok’ status. On the other hand, for 2 bit error during Synchronous Burst Block Read, ECC correction is not possible, and Controller Status Register(F240h) will show ‘load fail’ status.

Note that for both cases, ECC Status Register(FF00h) value will remain the same at value of 0000h.

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