Address Setting

ADQ0~

. . A1

 

1st data input

ADQ15

 

 

 

 

4KB data into 2 DataRAMs

High-Z

A2 2nd data input

4KB data into 2 DataRAMs

. . . . . An Last data input

4KB data into 2 DataRAMs

6.15 2X Interleave

MuxOneNAND2G(KFM2G16Q2A MuxOneNAND4G(KFN4G16Q2A

Ongoing

Chip1 Status

INT bit

{

 

 

 

 

 

 

 

 

 

 

 

 

 

 

. . .

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2X cache program

 

Command

 

 

2X Cache program

 

Command

 

 

2X program

 

Command

 

 

 

 

 

Controller Status

 

Register Check

 

 

 

 

 

 

 

 

Controller Status Register Check

 

 

 

Plane1 / Plane2 current : Invalid (Fixed to 0)

Plane1 / Plane2 current : Invalid

 

 

 

Plane1 / Plane2 previous: Invalid (Fixed to 0)

Plane1 / Plane2 previous: Pass=0, Fail=1

 

 

 

Address Setting

Controller Status Register Check Plane1 / Plane2 current : Pass=0, Fail=1 Plane1 / Plane2 previous: Pass=0, Fail=1

Cache Program

- -

- 158 -

ADQ0~

ADQ15

Ongoing

Chip2 Status

INT bit

. . . . . . . A1

 

 

 

 

A2

 

 

 

. . . . . An

 

 

1st data input

 

2nd data input

Last data input

 

 

 

4KB

 

data into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4KB data into

 

 

 

 

4KB data into

 

 

2 DataRAMs

 

 

2 DataRAMs

 

2 DataRAMs

. . . . .

 

. . . . .

. . .

2X cache program Command

2X Cache program Command

2X program Command

Controller Status Register Check

Controller Status Register Check

Controller Status Register Check

Plane1 / Plane2 current : Invalid (Fixed to 0)

Plane1 / Plane2 current : Invalid

Plane1 / Plane2 current : Pass=0, Fail=1

Plane1 / Plane2 previous: Invalid (Fixed to 0)

Plane1 / Plane2 previous: Pass=0, Fail=1

Plane1 / Plane2 previous: Pass=0, Fail=1

Operation Timing

DEBx) DEBx)

INT Pin

 

 

 

 

 

 

 

 

 

. . .

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1, A2, A3 : Address of DataRAM to be written.

INT: Indicator for DataRAM’s Status (Ready=High, Busy=Low)

Ongoing Status : Indicated by OnGo bit in Controller Status Register [15] (F240h)

4KB data input : Asynch Write / Synch Write available.

Command input and INT bit or pin behavior is based on ‘INT auto mode’.

NOTE :

1) INT pin might toggle when INT bit of chip1 turns to ready before host issues ‘2X program’ command on chip2.

FLASH MEMORY

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Image 158
Samsung KFM2G16Q2A, KFN4G16Q2A warranty 15 2X Interleave, Cache Program, ADQ0~ ADQ15