Samsung KFM2G16Q2A, KFN4G16Q2A ......, .., ...

MuxOneNAND2G(KFM2G16Q2A-DEBx)

- 157 -

FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

6.14 2X Cache Program Operation Timing

1st data input 2nd data input

2X cache program Command

ADQ0~

A1, A2, A3 : Address of DataRAM to be written

INT: Indicator for DataRAM’s Status (Ready=High, Busy=Low)

Ongoing Status : Indicated by OnGo bit in Controller Status Register [15] (F240h)

4KB data input : Asynch Write / Synch Write available.

Command input and INT pin behavior is based on ‘INT auto mode’.

In ‘INT manual mode’, writing ‘0’ to interrupt register is required before command issue.

ADQ15 A1 A2

High-Z

INT

........

4KB data into

2 DataRAMs

4KB data into

2 DataRAMs

2X Cache program Command 2X program Command

3nd data input

A3

4KB data into

2 DataRAMs

...

O

ngoing

S

tatus

Controller Status Register Check

Plane1 / Plane2 current : Invalid

Plane1 / Plane2 previous: Pass=0, Fail=1

Controller Status Register Check

Plane1 / Plane2 current : Pass=0, Fail=1

Plane1 / Plane2 previous: Pass=0, Fail=1

Controller Status Register Check

Plane1 / Plane2 current : Invalid (Fixed to 0)

Plane1 / Plane2 previous: Invalid (Fixed to 0)

Contents

Main MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) KFM2G16Q2A KFN4G16Q2A 2Gb MuxOneNAND A-die MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Revision History Document Title MuxOneNAND Revision History Page MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.0 INTRODUCTION 1.1 Flash Product Type Selector 1.2 Ordering Information 1.3 Architectural Benefits KF X XX 16 Q 2 A - D E X X MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.4 Product Features 1.5 General Overview 2.0 DEVICE DESCRIPTION 2.1 Detailed Product Description 2.2 Definitions 2.3 Pin Configuration 2.3.1 2Gb Product (KFM2G16Q2A) 2.3.2 4Gb Product (KFN4G16Q2A) 2.4 Pin Description 2.5 Block Diagram 2.6 Memory Array Organization 2.6.1 Internal (NAND Array) Memory Organization Sector Block Page 2.6.2 External (BufferRAM) Memory Organization Host External (BufferRAM) Memory Internal (Nand Array) Memory { { MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7 Memory Map 2.7.1 Internal (NAND Array) Memory Organization Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 2.7.2 lnternal Memory Spare Area Assignment 2.7.3 External Memory (BufferRAM) Address Map 2.7.4 External Memory Map Detail Information 2.7.5 External Memory Spare Area Assignment Page Page 2.8 Registers 2.8.1 Register Address Map 2.8.2 Manufacturer ID Register F000h (R) 2.8.3 Device ID Register F001h (R) Page 2.8.6 Boot Buffer Size Register F004h (R) 2.8.7 Number of Buffers Register F005h (R) 2.8.8 Technology Register F006h (R) 2.8.9 Start Address1 Register F100h (R/W) 2.8.10 Start Address2 Register F101h (R/W) 2.8.11 Start Address3 Register F102h (R/W) 2.8.12 Start Address4 Register F103h (R/W) 2.8.13 Start Address5 Register F104h (R/W) 2.8.14 Start Address6 Register F105h 2.8.15 Start Address7 Register F106h 2.8.16 Start Address8 Register F107h (R/W) 2.8.17 Start Buffer Register F200h (R/W) { { 2.8.18 Command Register F220h (R/W) 2.8.18.1 Two Methods to Clear Interrupt Register in Command Input 2.8.19 System Configuration 1 Register F221h (R, R/W) Page Page Page 2.8.20 System Configuration 2 Register F222h 2.8.21 Controller Status Register F240h (R) Page Page Page Controller Status Register Output Modes Controller Status Register Output Modes (Continued) 2.8.22 Interrupt Status Register F241h (R/W) Page 2.8.23 Start Block Address Register F24Ch (R/W) 2.8.24 End Block Address Register F24Dh 2.8.25 NAND Flash Write Protection Status Register F24Eh (R) 2.8.26 ECC Status Register FF00h (R) 2.8.27 ECC Result of 1st Selected Sector, Main Area Data Register FF01h (R) 2.8.28 ECC Result of 1st Selected Sector, Spare Area Data Register FF02h (R) 2.8.29 ECC Result of 2nd Selected Sector, Main Area Data Register FF03h (R) 2.8.30 ECC Result of 2nd Selected Sector, Spare Area Data Register FF04h (R) 2.8.31 ECC Result of 3rd Selected Sector, Main Area Data Register FF05h (R) 2.8.32 ECC Result of 3rd Selected Sector, Spare Area Data Register FF06h (R) 2.8.33 ECC Result of 4th Selected Sector, Main Area Data Register FF07h (R) 2.8.34 ECC Result of 4th Selected Sector, Spare Area Data Register FF08h (R) Page 3.0 DEVICE OPERATION 3.1 Command Based Operation 3.1.1 Reset MuxOneNAND Command 3.1.2 Load MuxOneNAND Command 3.1.3 Read Identification Data Command 3.2 Device Bus Operation 3.3 Reset Mode Operation 3.3.1 Cold Reset Mode Operation 3.3.2 Warm Reset Mode Operation 3.3.3 Hot Reset Mode Operation 3.3.4 NAND Flash Core Reset Mode Operation 3.4 Write Protection Operation 3.4.1 BootRAM Write Protection Operation 3.4.2 NAND Flash Array Write Protection Operation 3.4.3 NAND Array Write Protection States 3.4.3.1 Unlocked NAND Array Write Protection State 3.4.3.2 Locked NAND Array Write Protection State 3.4.3.3 Locked-tight NAND Array Write Protection State 3.4.4 NAND Flash Array Write Protection State Diagram * Samsung strongly recommends to follow the above flow chart * DFS, DBS is for DDP (DFS must be same) * DFS, DBS is for DDP (DFS must be same) 3.5 Data Protection During Power Down Operation 3.6 Load Operation 3.7 Read Operation 3.7.1 Asynchronous Read Mode Operation (RM=0, WM=0) 3.7.2 Synchronous Read Mode Operation (RM=1, WM=X) 3.7.2.1 Continuous Linear Burst Read Operation * Reserved area is not available on Synchronous read 3.7.2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation 3.7.2.3 Programmable Burst Read Latency Operation 3.7.3 Handshaking Operation 3.7.4 Output Disable Mode Operation 3.8 Cache Read Operation (RM=X, WM=X) Page Finish 3.9 Synchronous Burst Block Read Operation(RM=1, WM=X) 3.9.1 Burst Address Sequence During Synchronous Burst Block Read Mode 3.9.2 Continuous Linear Burst Read Operation During Synchronous Burst Block Read Mode { 3.9.4 Programmable Burst Read Latency Operation During Synchronous Burst Block Read Mode 3.9.5 Handshaking Operation During Synchronous Burst Block Read Mode 3.10 Synchronous Write(RM=1, WM=1) 3.11 Program Operation Page 3.11.1 2X Program Operation Page 3.11.2 2X Cache Program Operation 2X Cache Program Operation Flow Diagram * * DBS, DFS is for DDP (DFS must be same) : 3.11.3 2X Interleave Cache Program Operation Chip2 Chip1 2X Interleave Cache Program Operation Flow Diagram Start * 3.12 Copy-Back Program Operation Page 3.12.1 Copy-Back Program Operation with Random Data Input 3.13 Erase Operation 3.13.1 Block Erase Operation * DFS is for DDP 3.13.2 Multi-Block Erase Operation 3.13.3 Multi-Block Erase Verify Read Operation *DBS, DFS is for DDP (DFS must be same) 3.13.4 Erase Suspend / Erase Resume Operation ** DBS, DFS is for DDP (DBS must be same) 3.14 OTP Operation Page 3.14.1 OTP Block Load Operation Add: F220h Page Page 3.14.3 OTP Block Lock Operation Page 3.14.4 1st Block OTP Lock Operation Page 3.14.5 OTP and 1st Block OTP Lock Operation DQ[6]=1(OTP ) 3.15 Dual Operations 3.15.1 Read-While-Load Operation 3.15.2 Write-While-Program Operation Page Write While Program Diagram Data PGM_PageA : Program Data from DataRAM to PageA PD_CMD : Program Command CMD_reg : Command Register Address Int_reg : Interrupt Register Address 3.16 DQ6 Toggle Bit 3.17 ECC Operation 3.17.1 ECC Bypass Operation 3.18 Invalid Block Operation 3.18.1 Invalid Block Identification Table Operation 3.18.2 Invalid Block Replacement Operation { ~ { 4.0 DC CHARACTERISTICS 4.1 Absolute Maximum Ratings 4.2 Operating Conditions 4.3 DC Characteristics 5.0 AC CHARACTERISTICS 5.1 AC Test Conditions 5.2 Device Capacitance CAPACITANCE 5.3 Valid Block Characteristics 5.4 AC Characteristics for Synchronous Burst Read 5.5 AC Characteristics for Asynchronous Read 5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset 5.7 AC Characteristics for Asynchronous Write 5.8 AC Characteristics for Burst Write Operation 5.9 AC Characteristics for Load/Program/Erase Performance 5.10 AC Characteristics for INT Auto Mode 5.11 AC Characteristics for Synchronous Burst Block Read 6.0 TIMING DIAGRAMS 6.1 8-Word Linear Burst Read Mode with Wrap Around 6.2 Continuous Linear Burst Read Mode with Wrap Around 6.3 Synchronous Burst Block Read Operation Timing See AC Characteristics table 5.4 and 5.7. t t t tCH tCS Page Page 6.5 Asynchronous Read (VA Transition Before AVD Low) 6.6 Asynchronous Read (VA Transition After AVD Low) 6.7 Asynchronous Write 6.8 8-Word Linear Burst Write Mode 6.9 Burst Write Operation followed by Burst Read 6.10 Start Initial Burst Write Operation 6.11 Load Operation Timing 6.12 Program Operation Timing 6.13 2X Program Operation Timing .... 6.14 2X Cache Program Operation Timing ...... tatus INT ADQ15 ADQ0~ { ...... Status Ongoing ... .. 6.16 Block Erase Operation Timing 6.17 Cold Reset Timing 6.18 Warm Reset Timing See AC Characteristics Tables 5.6. 6.19 Hot Reset Timing See AC Characteristics Tables 5.6. RDY Operation or Idle MuxOneNAND reset Idle MuxOneNAND Operation 6.20 NAND Flash Core Reset Timing 6.21 Data Protection Timing During Power Down 6.22 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low) 6.23 Toggle Bit Timing in Asynchronous Read (VA Transition After AVD Low) 6.24 INT auto mode See AC Characteristics Tables 5.10. tWB 7.0 TECHNICAL AND APPLICATION NOTES 7.1 Methods of Determining Interrupt Status 7.1.1 The INT Pin to a Host General Purpose I/O INT COMMAND 7.1.2 Polling the Interrupt Register Status Bit INT 7.1.3 Determining Rp Value (DDP, QDP only) INT pol = High (Default) INT pol = Low 7.2 Boot Sequence 7.2.1 Boot Loaders in MuxOneNAND 7.2.2 Boot Sequence Partition of NAND Flash array Internal BufferRAM MuxOneNAND Boot Sequence NAND Flash Array 8.0 PACKAGE DIMENSIONS 2G product (KFM2G16Q2A) 4G product (KFN4G16Q2A)