MuxOneNAND2G(KFM2G16Q2A-DEBx)

FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

7.1.2 Polling the Interrupt Register Status Bit

An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT pin.

When using interrupt register instead of INT pin, INT pin is recommended to float to avoid power consumption at IOBE=0(disable).

Command

INT

This can be configured in either a synchronous mode or an asynchronous mode.

Synchronous Mode Using Interrupt Status Register Bit Polling

When operating synchronously, CE, AVD, CLK, RDY, OE, and DQ pins on the host and MuxOneNAND are tied together. RDY could be connected as one of following guides.

Host

CE

AVD

CLK

RDY(WAIT)

OE

DQ

MuxOneNAND

CE

AVD

CLK

RDY

OE

DQ

Host

CE

AVD

CLK

OE

DQ

MuxOneNAND

CE

AVD

CLK

RDY

OE

DQ

Handshaking Mode

Non-Handshaking Mode

Asynchronous Mode Using Interrupt Status Register Bit Polling

When configured to operate in an asynchronous mode, CE, AVD, OE and DQ of the MuxOneNAND are tied to corresponding pins of the Host. CLK is tied to the Host Vss (Ground). RDY is NOT connected.

Host

CE

AVD

Vss

OE

DQ

MuxOneNAND

CE

AVD

CLK

RDY

OE

DQ

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Image 168
Samsung KFM2G16Q2A, KFN4G16Q2A Polling the Interrupt Register Status Bit, Handshaking Mode Non-Handshaking Mode, 168