Samsung KFM2G16Q2A, KFN4G16Q2A warranty OTP Block Load Operation, 122

MuxOneNAND2G(KFM2G16Q2A-DEBx)	FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)

3.14.1 OTP Block Load Operation

An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer, thus making the OTP contents available to the Host.

The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of a Flash Block Address (FBA) command.

After being accessed with the OTP Access Command, the contents of OTP memory area are loaded using the same operations as a normal load operation to the NAND Flash Array memory (see section 3.6 for more information).

To exit the OTP access mode following an OTP Block Load Operation, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is per- formed.

OTP Block Read Operation Flow Chart

Start

Select DataRAM for DDP

Add: F101h DQ=DBS*

Write ‘DFS*, FBA’ of Flash1)

Add: F100h DQ=DFS*, FBA

Write 0 to interrupt register2)

Add: F241h DQ=0000h

Write ‘OTP Access’ Command

Add: F220h DQ=0065h

Wait for INT register low to high transition

Add: F241h DQ[15]=INT

Write ‘FPA, FSA’ of Flash

Add: F107h DQ=FPA, FSA

Write ‘BSA, BSC’ of DataRAM

Add: F200h DQ=BSA, BSC

NOTE :

Write 0 to interrupt register2)

Add: F241h DQ=0000h

Write ‘Load’ Command

Add: F220h

DQ=0000h or 0013h

Wait for INT register low to high transition

Add: F241h DQ[15]=INT

Host reads data from

DataRAM

OTP Reading completed

Do Cold/Warm/Hot

/NAND Flash Core Reset

OTP Exit

*DBS, DFS is for DDP (DBS and DFS must be 0)

1)FBA(NAND Flash Block Address) could be omitted or any address in a single die package.

FBA must be an address of a chip containing OTP block that is supposed to be accessed in DDP

2)‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1.

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