Samsung KFM2G16Q2A 2X Interleave Cache Program Operation Flow Diagram Start, For a chip, 112

MuxOneNAND2G(KFM2G16Q2A-DEBx)	FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)

2X Interleave Cache Program Operation Flow Diagram

Start

Select DataRAM for DDP1)

Add: F101h DQ=DBS

Write Data into DataRAM0,1

Add: DataRAM DQ=Data(4KB)

Write ’DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA2)

Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA3)

Select DataRAM for DDP1)

Add: F101h DQ=DBS

Check INT register

if it is ready5)

Add: F241h DQ=8040h

Read Controller

Status Register

Add: F240h DQ[4],[2]=Plane1,2 previous

NO

DQ[4] DQ[2] = 0?

Select DataRAM for DDP1)

Add: F101h DQ=DBS

Check INT register

if it is ready5)

Add: F241h DQ=8040h

Read Controller

Status Register

Add: F240h DQ[4],[2]=Plane1,2 previous

NO

DQ[4] DQ[2] = 0?

NO

DQ[10]=0?

YES

Select DataRAM for DDP1)

Add: F101h DQ=DBS

Check INT register

if it is ready5)

Add: F241h DQ=8040h

Read Controller

Status Register7)

Add: F240h DQ[10]=Error

Write ’BSA’, ’BSC’ of Flash3)

Add: F200h DQ=BSA, BSC

Write 0 to Interrupt register4)

Add: F241h DQ=0000h

NO

YES

Last 2 Plane PGM

for a chip?

YES

YES

Write Data into DataRAM0,1

Add: DataRAM DQ=Data(4KB)

NO

DQ[10]=0?

YES

Write 2X Cache PGM CMD

Add: F220h DQ=007Fh

Is it first input	NO
for a chip

YES

*DBS, DFS is for DDP

*If program operation results in an error,

map out the block including the page in error and copy the target data to another block.

Write Data into DataRAM0,1 Add: DataRAM DQ=Data(4KB)

Write ’DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA2)

Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA3)

Write ’BSA’, ’BSC’ of Flash3) Add: F200h DQ=BSA, BSC

Write 0 to Interrupt register4)

Add: F241h DQ=0000h

Write 2X PGM CMD6) Add: F220h DQ=007Dh

Write ’DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA2)

Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA3)

Write ’BSA’, ’BSC’ of Flash3)

Add: F200h DQ=BSA, BSC

Write 0 to Interrupt register4)

Add: F241h DQ=0000h

Write 2X PGM CMD6) Add: F220h DQ=007Dh

Wait for INT register

low to high transition4)

Add: F241h DQ=8040h

Read Controller

Status Register7)

Add: F240h DQ[10]=Error

complete

Map Out

NOTE :

1)DBS must be set before data input.

2)FBA must be an even block.

3)These registers must be set as BSA=1000, BSC=00 and FSA=00.

4)‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1.

5)Host is strongly recommended to see the INT register(F241h) of each chip.

6)Once ‘2X PGM command’ is issued onto a chip, the same command(2X PGM) must be issued onto another chip. If not, Samsung can not gurantee the following operation.

7)If error bit is set at this step, DQ[1]~[4] shoulde be checked in order to find where the error occurred.

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