TDK 750W HALF RACK technical manual Fault Enable Register, Fault Event Register

The SRQ message is: “Inn” terminated by CR, where the nn is the power supply address. The SRQ will be generated either in Local or Remote mode.

Refer to Tables 7-10 to 7-13 for details of the Enable and Event registers.

1. Fault Enable Register

The Fault Enable Register is set to the enable faults SRQs.

Table 7-10: Fault Enable Register

BIT	Enable	Fault symbol	Bit Set condition	Bit reset condition
	bit name
0 (LSB)	Spare bit	SPARE
1	AC Fail	AC		User command: “FENA nn”
			User command:	where nn is hexadecimal (if
2	Over Temperature	OTP
			“FENA nn” where	nn=”00”, no fault SRQs will
3	Foldback	FOLD	nn is hexadecimal	be generated).
4	Over Voltage	OVP
5	Shut Off	SO
6	Output Off	OFF
7(MSB)	Enable	ENA

2. Fault Event Register

The Fault Event will set a bit if a condition occurs and it is Enabled. The register is cleared when FEVE?, CLS or RST commands are received.

Table 7-11: Fault Event Register

BIT	Enable	Fault symbol	Bit Set condition	Bit reset condition
	bit name
0 (LSB)	Spare bit	SPARE
1	AC Fail	AC	Fault condition	Entire Event Register is
			occurs and it is	cleared when user sends
2	Over Temperature	OTP
			enabled.	“FEVE?” command to read
3	Foldback	FOLD	The fault can set a	the register.
			bit, but when the	“CLS” and power-up also
4	Over Voltage	OVP
			fault clears the bit	clear the Fault Event Reg-
			remains set.	ister. (The Fault Event
5	Shut Off	SO
				Register is not cleared by
				RST)
6	Output Off	OFF
7(MSB)	Enable	ENA

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83-507-5002 Rev. B