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storedin the displayshift register.Then,as th€ A value is-read.itis cornparedwith the B valueand the larger of the two is loaded into the disptay shift regisier. Finally,the numberin the shift registei is writte; into memory.This operationis performedonce each time thatth€ save A modeis selected.

Vertical control lC U2090 contains a 3-bit synchro_ nous counterthat id€ntifiesthe specificbit of in g,bit verticalvaluethat is to be read from memoryor written intomemory.This is the onlymemoryaddressingthat is performedby U2030.All other addrdssingis performed !y tne horizontatcontrol lC (on the HoiizontatDigital Storageboard).

Dlgltzlng Clrcults. The input vertical signat, VtD FLTROUT, coupledthroughedge connectorpin 60 is appliedthroughbufferU3040to sampteand hoidswitch U2040C.U2040C is controiled by frip-flop U10108. U10108 generatesthe sample puise, and is enabled 9uljng the ctock cycte after tne iast approximation,as indicatedby the leastsignificantbit trom the successive approximationregisterin U2030.The switchedsample is thenappliedthroughbufferU1045to a summingjunc_ tion. At this point the output current from Oigitifto- analogconverterUg02S,that is suppliedfrom the suc_ cessiveapproximationregisterin Ui03O,is subtracted from the samplecurrent.The differencecurrentis then fpRlieOthr-o-ughcomparatorU2O3SBand synchronizing flip-flop,y:2027A,to pin 18 of U2030as th; UpiDowti slOnal. The binary equivatentof the input sample is sfiectivelyproducedby the combinationof the succes- sive approximationregister, the digital_to-analogcon_verter,andthe sampleand holdcircuit.

Address Decoding. The address decode logic accepts inputs from the address bus and trom the addresscontrollogic on the HorizontalDigitalStorage board,producingthe control signalsfor read and wri-teoperations:

CONTW (controlwrite)

DATAW (datawrite)

DATAR (dataread)

The controlwrite signalgatesthe controlword from the data bus into control register UZOZ'to generate modecontrolsignals.This controlword consistsof one bit, 04, that representsthe front-panelMAXHOLDfunc-tion. lf outputQ5 is low, a peak operationis forced;if outputQ5 is high and e6 is low, an averageoperation is forced. The data read and data write signals are appliedto the interfacelogic to control memory read andwriteoperations.

Theory of Operatlon- 494A/4g4ApServlce,Vol. I

InterfaceLogic.The interfacelogic,in general,per- forms control and interfacefunctionsbetweenthe active data circuitsin the verticaland horizontalsectionsand the rest of the instrumentlt. allowsthe microcomputer to control the storagesystemfunctionsand to access the digitalstoragememory.lt alsocontainsth€ circuitry for serial-to-paralleland parallel-to-serialconv€rsion. (l'hemicrocomputeruses paralleltransfer; the digital :lollSe memory uses seriat transfer.) Shift regaster U4020reads data from memoryto the data bus. Regis- ter U2025 stores information from the data bus for transfer to memory. Multiplexer U40i5 does the parallel-to-serialconversionand appliesthe dataoutput to gate U30248,whichacts as a bufferto supplyeitirer the multiplexeroutput or the MEM OUT (memoryout_ put)signalfrom U2030to the memoryas the DSDa(digi- tal storagEdata Input)data train.

The interfacecircuit group on the Vertical Digital Storage board is the handshaketogic that works with the horizontalcontrolcircuitsto accessth€ mernoryand to determinewhen to incrementthe memoryaddress counter.In either a data read or data write operation (when th€ correspondingsignal goes high), flip-flop U30208is triggered.This reteasesthe BUS REe (bus request)line to allowthat signalto go high and signats the horizontalcontrol circuit that memory access is required.When th€ horizontalcircuits recognizethe request.thos€ circuitspullthe BUS REOline low at the sametime that SYNCis low. The interfacelogicdetects

the BUS REQand SYNClow conditionthroughU201SA, U20158,U3010A,and U3015A,and producesthe tow BUS GRANT signal to indicatememory access. The BUSGRANTsignalthenenablesshiftregisterU4020to shift data from memoryor enableregisterUl02l . BUS GRANTalso enablesmultipl€xerU401Sto Ehlftdatato memoryas indicatedby the DATAR and DATAW tines.

At the end of a data read cycle, gates U2010Band U4030Cproduce the INCR ADRS (incrementaddress)

signalto incrementthe addressregisterin the horizon- tal circuits.

MaximumHold. As describedpreviously,whenthe Max Hold mode is selected,the signalfrom e4 of con- trof registerV2428causesth€ circuitsin Ul023 to com- parethe binaryequivalentof th€ inputsignalfor a giv€n

Xvaluewith the informationin memoryfor that sameX value.This causesthe larger value of the two to be stored in memory.The signalfrom 04, in combination with the VALID signalfrom the horizontalcircuits,pro- duces the MAX HOLD command to U2090 through inverterU4030Eand gateU4040A.

ConstantCircuit As describedpreviously,in the B minusA operation, constantis used.Thisconstantis selectedinternallywith switch31015, This switch,in

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