Tektronix 494AP service manual O o a O o o, Figure Z-2S. DAC Varlance graph

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incremented.Thus,the two mustappearas follows:

Upperorder
1 0 0 00 0 OOO1 0 O
Lower order	0 1 ' l1 1 1 1 1 1 1 1 1

lf the high-orderdevice operated with no overatl linearity inaccuracy,the operation would now be com- plet€ and the low-order incrementingcould occur. However,th€ DAC devicecan vary byine LSB of the correct value. Figure 7-25 illustrltei a graptr of the b€st and worst case output. Not€, that-even in the worst case, the output may move onty once every two or threestate changes,_butthe outpuf is alwaysmono_ tonicand within one LSB of the correct value.

t - - - ;	WORST-CASE
i l	OUTPUT

-r-]*BEST- .CASEOUTPUT

Mr6.124

Figure Z-2S. DAC Varlance graph.

ff, In the exampleshown previously,th€ high-orderdevice is at point A in Figure 7-25, incrementingthe device to point B has no effect on the output. lf the MSBof the low-orderdeviceis set to zero,as shownin the first example, the combined output will actually de.crease-Ordinarily,the CenterFrequencyControlcir- cuit can incrementand decrementwheneverthe micro_ computer commandswithout going through a special routine. However,as just described,some microcom- puter adjustmentis necessaryto compensatefor the disparitythat usuallyoccursbetweenthe low-orderandhigh-orderDACunits.

The first operating mode is the tracking mode, where the preamplifierand integratorare connected together by the disconnectstage, and the entire unit acts as an operationalamplifier. FigureZ_26illustrates

Theoryof Operation- 4g4Ll4g4ApServlce,Vol. 1

the basic clrcuit. Whil€ the circuit opgrates in this mod€,the amplifiertracksthe DACstageand sendsthe voltageout to the tuningcircuits.

When the transfer of bits from the lowgr to the upper DAC ls required,the microcomputercommancls the circuit to shift to the hold mode. Th€ command comes throughthe decoderto shut off the disconnect stage.and the preamplifieroutputis disconnectedfrom the integrator. Th€ integrator holds th€ voltage that was previouslyat the output for comparison,and the approximationcyclebegins.

The microcomput€rresets the low-orderDAC to zero. Then,th€ highestorder bit in the low-orderDACis set to one, and th€ circuit is queriedto find if the DACoutputand integratoroutputis greateror lessthan required. lf less. the microcomput€rloads the next lower bit in additionand queriesthe circuitonce more. This processgoeson untilthe two valuesarethe same. Had th€ microcomputerfoundthat the DACoutputwas greaterthan the integratoroutput at the first inquiry,it wouldhaveset the highestordErbit to zero and loaded the second-orderbit into the low-orderDAC.then con- tinued to load successivelylower order bits, one at a time, until the circuit signaledthat the comparisonhad reversed. By this process,which is knownas the suc_ cessive approximation method, the circuit finally reachesthe point wherethe outputsare €qual,and th6 microcomputercommandsthe circuit to shift back to the trackmode.

Digital Control

The digitalcontrolcircuits consistof bufferU4Og5,

addressdecoder U4045,steeringregisterU4025,and the steeringgates(U4015A,U40158,U401SD,U4O6OA. U4060B,and U4060D).Becauseof the largeamountof

data that must pass throughthese circuits,a steering registerthat hasa separateaddressis used.

The steeringbyte,is clockedinto U402Sat addr€ss

70.The outputsare appliedto the steeringgates,and the circuitwaitsfor the next byte.

The microcomputerthen furnishesthe first byte ol data to be sent to the low-order.fine-tune,DACvia the storageregister. Latch u3015 and part of U3025form one storageregisterfor the low-order,fine-tuneDAC. The byte is clockedinto the registerby the coincidence of low statesat the inputsof the steeringgate(u4015A or U4015B); one from the st€eringbyte and the other from ADDRESS71 signal,which is usedto clock the steereddata bytes into the correctregister. This con- tinuesuntil sevenbytesof data haveb€en clockedinto the register.includingthe steeringbyte.

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