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GPIA interfacecircuit on th€ GptB board (A56). (Ihis onlyoccurson the programmable

version.)

Before each transf€r, the microprocessorloads U1020with the startingaddressof the RAM data and the numberof data bytesto be transferred.Whenthe GPIA interfacecircuit requiresdata, it pulls the DMA Requestline, pin 4 of pl03S, low. Thisiauses U1O30C to set U1020'sTransferfiequestinputhigh,requesting a byte. ln rEturn,the DMA ControllerienOs a DIUA requestto the processor,sHALT input, pullingit low. This also disablesany maskabteinterruptiequestto tne processor. With HALT low, the microprocessorcom- pletesits currenilyexecutingInstructionandthenstops, signalsthat the bus is avaitabte(setsthe BA tinehigh), tri-statesitsdata bus, and sets itselfin the Readstlte (RflrVline high).

The BA signaldisablesthe rnicroprocessoraddress bufrers,U3030and U302S,and enablesDMA Controller accessto the address bus via bufferU1024and tran_ sceiverU1015. lt also givesbus controlto the DMA Controller.The least significantaddresslinesare inter- faced to Ul020 througha transceiverbecausethe pro- cessor uses addressesA0 throughA4 to addressthe setupregistersin the DMAcontroller.

The DMA Controllersets th€ address,VMA, and ReadfA/rite(RflrV)lines to caus€the RAM to plac€ the proper byte on the data bus. BecauseU10b0 is an open-collectorgate, there is no conflict betweenthe microprocessorand the DMA Controllerover the R/W line.

The DMA ControilerTransferStrobetIxSTB) output goeslow givingthe DMAGRANTsignaltotne eFte fir_ cuit on the GPIB board. This infoimsthe circuit that datais coming. Afterthe transferis completed,UlO20 raises the HALT line, and normalprocessoroperation resumes.

Groundfrom the GplB boardconnectsthroughpin 2 of P1035 as a signal that the processor and GplB boards are connected. lf the GplB board is not

present,suchas for testpurposesr pin U10gSB 12 goes

low. This disablesthe DMArequest.

Interrupt Processing. The microprocessoruses both maskableand non-maskableinterrupts. The non_ rnaskableinterruptis used only for sensingpower-fail. The maskable interrupt is used to seise circuits requestingservice. Althoughthese interruptsmay be rnaskedby the processor,they are enabledmostof the time. These interruptscan be requestedbv circuitson the InstrumentBus, the GplB board,the DMA con- troller,or the Timer. The instrumentfirmwarecontains

Theory of Operation- 494A/4g4ApServlce,Vol, I

serviceroutinesfor eachof the interrupts.

The maskable interrupts are sensed at the microprocessor'sInterruptRequest(lRQ) input. Gate u2036 sets IRQ low if it senses any of the int€rrupt lineslow. The Inputport bufferU3O2Oplacesthe inter- rupt infornationand swe€panformationon the databus. This allows the microproc€ssorto read the int€rrupt status.

lf the interupt is from circuits on the Instrument Bus, the microprocessorexecutes a poll routine to determinethe exact causeof the interrupt. The Instru- ment Bus circuitsinterruptthe microprocessorby pul_ ling the Service Request(SER REO or SR) tine tow. The microprocessorrespondsby placingaddressFF on the InstrumentBus and setting the OATA VALIDanct POLL signals high. This causes the circuit that requestedserviceto pull one of the datalineslow.

Eachcircuitis assigneda differentline,as shownin Table 7-22.lt is possiblethat more than one circuit requ€stsserviceat th€ same time. In that case.more thanonedata linewill be low.

The microprocessorreads the data lines to deter_ mine the interruptingcircuit or circuits. tt then writes the corespondingbit patternto the data bus whil€the addresslinesare set to ZF and DATAVALIDand pOLL

are both high. When an interruptingcircuit receivesa low on its assigneddata line with the addresslines, DATAVALID.and POLL set as described,it rgsetsits internalinterruptlatchand releasesthe ServiceRequest (setssER REQor SRhigh).

	Table 7-22
	POLLBITS
Bit 7	Not Used
Bit 6	Not Used
Bit 5	Not Used
Bit 4	End of Sweep
Bit 3	FREQUENCYknob
Bit 2	Phase Lock
Bit 1	Not Used

0Front Panel

The non-maskableinterruptsignalspowerloss. Cir- cuitryon the Z-Axisassembly(A70)sensespowerloss and setsthe PWRFAILlinelow. This causesan inter- rupt andstartsthe microprocessor'spowerfail routine.

Wh€n PWR FAIL goes low, e2030 turns on and C2030beginsto dischargethroughRl032. tf the tine stayslow until C2030discharges,the RESETline goes low and the microprocessorres€ts itself. As part of its power fail routing, the microprocessormonitors the PWRFAIL, along with other interupts, throughU9020.

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