Tektronix 494AP service manual Phaselocksynthesizer Diagrams39

DBl-ThE N LATCHsignatfor the lst LO phasetock is senton this line.

DB2-Reservedfor futureapptications.

DB3-This lin€ resets the buffer sequencerat the outsEtof a talk cyclefor the counters.

DB4-This tine(CONTROL

LATCH)tatchesa conrrot word into the output buffers ot VZOZSon the Error Amplifierboard.

DBS-Thissignalclearsall the counterstagesin the counter- buffer circuits in preparation ,or a count sequence.

DB6-Thislinetatchesthe N data in Ul022.

DB7-Thisline is used as a clock to step data into U1422and U304gA,and for the data sent in the 1st LO phasetock. R3012and G2010act as a delayto provjdeadequatesetuptim€ for the datapriorto the clock signalarriving.

Buffers U3094, UgOgO,and U2026 are the tatk buffers that send data to the microcornputer.UgOlg and -U2030Amake up a step-enablerthat enablesthe talk bufrersone at a timewhen requestedby the micro- computer.

Input Ampliflers and Multiptexer

, Q1018bringsthe-5dBm,16 MHzto 20 MHzsignal f.r9T-tl9 2nd LO up to TTL tevets. U2010dividesthe 16-20MHzby 32 and 256 before it sends it to mutti- plexerUl018. U2056amptifiesthe _50 dBm,10 MHz lF. L2056anctC2056act as a 10 MHz bandpassfitter on th€ input of u2056. R3056providescurrentto the open_collector output of U2056. C3OS2couples the !!^UHz signatinto U4056. U4056acts as a dlvide-by- 128counter.Thesignatthengoesto U101g.

All-oth€rinputsignalsare at TTL levelsandare con- necteddirecflyto U101g. The ouputof U3010Ais con_ nectedto U1018so that the clock can be countedfor diagnosticpurposes.UlO1g selectsone of its inputs accordingto the datain U1022.

+2n Counter

The outputof U1019goes into a seriesof dividers made up of U1050 and U2050A. Variousoutputs of these dividersar€ connectedto multiplexerUl046 to givea +2ncounterwhere- 1,2, a,6, g, i0,11, ori2 (n is sel€ctedby the data stored in U1022).A strobe input to U1046disablesthe multiplexerwhen pulled high.

Theory of Operation- 4g4A/4g4ApSeMce, Vol. 1

21-Bit Counter

The 21-bitcounter counts the 1OOMHz reference frequencyto give a mgasursrnentof the time required to completea given numberof cycles of the selected input signal. The counter itself consists of UlGlg, U2018,U1028,and U2034. Ul0gg is an ECL divider. Q1034and Q1044are ECL-Io-TTLtranslatorsfor the +2 and +4, respectively.The +4 go€s to U20lg whereit is countgdwith TTL dividers.and the divider chain contin_ ues through U2034. The output of each stage goes to an output buffer so the rnicrocomputercan read th€ final numberof counts. Therefore,the microcomputer measuresthe time periodduringwhichthe counterwas enabfed. The counteris €nabtedby U20508 and rJ2046 for a ^timeperiod equal to eight cycles of the output of the +2ncounter.

At the start of a count, the microcomputerselects the input signalto be countedand sets ttre 'n'

number for thE -r2ncounter. The COUNT/RESETtine is then pulled high to reset alt of the countErs. U2046A is presetwith Q in the high$tate,whichdisablesthe 21_bit counter. The COUNT/RESETtine then goes high to start th€ measur€mentprocess, Th€ output of U1046 goes to U20508where it is further divideddown. On the first risingedge at pin 11 of U20508,Q of u2046A goes low to start the 21-bit counter. on the eighth count of u20508, u2046A steps back to its original state,whichstopsthe 21-bitcounter. At the sametirne, U20468pullsthe strobeto the +2ncounterhighto stop any furthercountsin U20508. The microcomputercan now readthe VALIDCOUNTlineto determinewhenthe countprocEssis completEd,and thenreadthe datathat is storedin the 21-bitcounter.

PHASELOCKSYNTHESIZER (Diagrams39 and 40)

The Phase Lock Synthesizerprovides frequency controland stabilityfor the lst localoscillator.The cir- cuit consists of the Synthesizerand phase Lock cir- cuits. The Phase Lock assemblyincludes the Error Amplifier, Offset Mixer, Controll€d Oscillator, and Strobe Driver. The Phase Gate Detector (shown on diagam36) is also part of the phaselock ciruitry.

Synthesizer (Diagram 39)

The Synthesizeruses the 100MHz referencefre- quencyfrom the 3rd Converterto generatethe 25 MHz referencefrequencyfor the OffsetMixer andthe +N fre- quency(determinedby the N numberfrom the proces- sor) for the phase/frequency

detector in the Offset Mixer. The +N frequencyis withinthe 32 kHz to 94 kHz range.

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