Tektronix 494AP service manual X x x x x x, X x o o o o o, X o o o o o, X . o o o o o, Xxxooooo

Theory of Operation- 494A/494ApService,Vot. 1

		COLUMN0.7
		0 1 2 3 4 5 6 7
	0 x x x x x x x x
	1 x x x o o o o o
IDLE	2	x x x o o o o o
POStTtON	J 3	x x x o o o o o
	8 4 x x x o o o o o
	E	x x x . o o o o o
	5
	6	xxxooooo
	7	xxxooooo

X: BLANK

O : DOT ON OR OFF

44rGl18

Figure 7-19. Charaeter scan.

The countersare wiredto torce the D/A converters to step throughthe characterhorizontally,a row at a time. At the sametime,the patternof dots is accessed underthe controlof the timingdecoderlogic, U2O39B and U2031. The AND gate and decoder combineto controf the character generator,U2048, which gen- erates the correct pattern of blankingto draw th€ pat- tern of dots for thEcharacter.U2048,the 8679charac- ter generatorlC (Figure7-20)containsa ROMwith the correct pattern of il bits for each of the 64 characters in its repertoire. The bit patternsare accessedby a decoderthat operateson the ASCIIcode on the charac- ter generatorinputs. The patternof bits is multiplexed, one 8-bit line at a time, into a shift register that is clockedout one bit at a timeto controlthe crt Z-axis.

CharacterGeneratorTiming.The charactergenera- tor timinglinesare calledDOT,LNECLK,LE.andCLR. Each cycle of DOT ctocksone dot (bio out of the shift register. A positivetransitionon LINE CLK switches the next line (row)of dots onto the shift registerinputs; the dots are latchedby a negativetransitionon LE (load enable),settingup the shift registerto displayanother row of dots. CLR resetsthe linecounterto begindraw- ing anothercharacter.

GEN RUNNING,INCR,and CRTCLK are combined throughANDgateUl0378 to generateDoT to clockthe character generator, U2048. lnversion by the gate restores the phase relationshipof the DOT input and the invertedLNE cLK. LE is gated by u203gBwhen

7-54

the charactercounterreachescolumn2. This loadsthe shift register with the next row of dots, which is displayedstartingat column3. LINECLK advancesthe line (row) counter after th€ scan of the current row beginsto set up the next row of dots on the shift regis- ter inputs; this occurs at column count 4. Decoder U2031 orrtputsa ROW 1 COL 1 when the character counterreachesrow 1, column 1 (the first non-blank row of dots scanned in each character). This is assertedonceduringthe scanof eachcharacter.

The sequenceof eventsto scana characteris illus- trated in the charactertimingdiagram(Figure7-211.At 1, the character generator ftnishesa character. Then, when the counter advances,decoder U2031 asserts ROW 0 COL 0, resettingthe GEN RUNNINGflip-flop, U10418,on the n€xt clock. Thig stops th€ count€rat row 0, column 1 (2 on the figure). When readout-ofi time one-shotUl055 completeslh€ time-outperiod,it allows the GEN RUNNINGftip-flopto b€ set. Just before the scan enters the actual characterclock area (at 6), CLR resets the charactergeneratorline count€r (at 5). LE (at 5a) loads one row of dots into the output shift registerso that the first dot is output at 6. The break(7 on the figure)indicatesthat the scancontinues. After the characteris scanned,the scan r€tums to the idle state;I and 9 correspondto 1 and 2 on the timing figure.

Dot Delay.Each bit shifted out of the charactergen- eratoris the valueof a dot in ths 5 x 7 charactermatrix:

0for a blankand 1 lor a dot that is to be written. As ths scan progressesat 3.4133MHz, a laint character display might be expected. To brightenthe dots that are written,a shift registeris used as a delayelement so that dots are displayedand countersdisabledfor 3 clockcycles.

Assume that no dots have b€en displayed for severaldot clock cycles,so the outputof the character generator,pin 11 of U2048,is low. Thus,U1020Bout- put is high, and the outputs of the delayshift register U1025Cand U10208are low. Whena dot is displayed, the charactergeneratoroutput (pin 11 of U2048)goes high. This causes INCR to go low and disable the counters. lt also causes the input to the delay shift register,pin 11 of U10208, to go high. On the next clock pulse,U10204outputfollowsINCRand goeslow. The shift register clocks the one in, and the unblank f,ip-flop,U10168,goes high, turningthe crt beam on. This is the only '1"it will clockin, becauseth€ outputof U1020Ais now low. ThE circuit is now in a lock-up state with the counters disabled. Two more clock cycles will go by until the "f in the shift register is clockedout, allowingthe output of U1033Cto go high.

Ahigh on the output of U1033Cstarts the counters againandresetsunblankflip-flopUl041A.

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