Tektronix 494AP O o A a a a o O o o, A o a o o o o, Centerfreouencycontrol DIAGRAM35

Theory of Operation- 494A/494ApServlce,Vol. 1

Current Driver

This stag€ consists of the output stage 0565/05052; FETs Q3061, eg077, and e2074: amplifiers U205,4and U3054; and transistor e4097. Whenthe Preselectoris not in use, DB2 goes low and turns Q2074ofi to reducethe coil currentto zero.

PreamplifierU2054reducesthe temperaturedrift of the output stage. DriverOfisetadjustment,R2066nuils the offsetvoltage(at whichpointthe temperaturedrift is feast). U2054drives amptifierU9054. A9061 isotates U3054from the output driverQ5052/O565.

GurrentamplifierQ5052drivesthe mainpreselector driver transistor, Q565. The stage ls biased so the currentdivides,with most of the currentgoingthrough the output transistor.and a lesser portionthroughthe bias circuits. Th€ curr€ntsrejoinat the preselector

coil. One set of terminalstor R4049carriesthe coit current. the other set sensesthe voltage.

When th€ DB5 line goes low, the preselectoris not swept, Q4037 and Q3077turn on, which adds C4071 across the Preselectorcoil to reducenoiseat the out- put.

Preselector Switch Driver

OperationalamplifierU10118and the complemen- tary pair of transistorsQ4025/4302Sform th€ preselec- tor switch driver. This circuit drives the filter select relaysshownon Diagram12. The relaysrequirea posi- tive pulse to selectthe Low-passFilter and a negative pulseto selectthe Preselector.

When the DB4 line goes high, a positivepulse of about 100 ms in duration, generat€d through RC differ€ntiatornetwork C3021/R302'1,isapptiedto the input of ul0118. The output of the operational amplifierdrops to about-12V and a positivepulse is passed through the transistorpair, selectingthe Low- pass Filter. When the DB5 line goes low, a negative pulseof the samedurationis passedto U10118.The amplifieroutput ris6s to about *12 V and a negative

pulse is passedthroughthe transistorpairto selectthe Preselector.

When the circuit is quiescentneither e3025 nor 04025 conduct,sincethe sum of the zenervoltagesot VR3011and VR3012is greaterthanthe combinedsup- ply voltages. When the output of the operational amplifiercomes near one of the supply voltages,the transistor, that is connected to the other supply, becomes saturat€d,and suppliesthe drive currentto actuatethe reiaycoil. CR4012and CR4013protectthe driver transistors from induced voltage surges and C3028and R3028dampenoscillationthat occur in the coil.

7-72

CENTERFREOUENCYCONTROL (DIAGRAM35)

The CenterFrequencyControl converts digital infor- mation,from the front panel FREOUENCYcontrol or on the GPIB bus, via the microcomput€r,to analog vol- tages for the 1st LO Driver and PreselectorDriver. These in turn control the center frequency of the analyzer.The CenterFrequencyGontrolboard contains ths tollowingmajorcircuits:

1.Tha Digital Control circuit, which buffers and decodesthe addressesand otherdatato controlthe othercircuits.

2.The coars€ and fine storage registers (latch€s), whibh store the numerical bytes that control the digital-to-analogconverter(DAC)stages. .

3.The coarse and fin€ DAC stages, which convert the digital inputs from the storage registers into analogcurent and voltageequivalentvalues.

4.The coarseand fine track/holdamplifiers,which stor€ the analogoutput valuesduring th€ approxi- mationroutineand comparethe storedvalueto the approximatedvaluefor the microcomputer.

5.The write-backcircuits.which informthe micro- computer when the stored value and th€ approxi- mat€dvalu€sare equal.

Operating Modes

An explanationof circuit design principlesis giv€n before the operationof the circuit is described. Two DAC chipsare usedin tandemto get the requiredreso- lution. However,this method can cause errors and non-monotonicbehaviorin the overallconvertercircuit. To circumventthis problem,the outputsof the tandem DAC units are summedtogether so that the two units are overlappedby three bits. That is, the MSB of the low-orderDAC is weightedequallywith the third least significantbit, or 2x10-to bit of the high order DAC. The overlap means that the lower DAC will have sufficientrange to monotonicallytune the output of the converteroverthe entirerangeof the analyzer,but only if the proper codes of the lower DAC device can be found. Now, supposethat the tandemDAC is loaded as follows:

Upperorder1 0 0 0 0 0 0 0 0 0 0 0

Lowerorder 1 1 1 1 1 1 1 1 1 1 1 1

The contents ol the devices are shown overlapped to illustrate the bit weighting. Now assum€ that the low-order device is to be incremented one bit. The MSB of the low-order device must be moved into the high-order device before the low-order device can be

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