Tektronix 494AP service manual DlclTAL STORAGEDiagrams25, Sytemis desisncto opn IT,r-.,.P.,9?

The filter consistsof resistors R2O2g,RZOZ1,R2022

and capacitorsC3026and C2016, between U3062and U2066.Tabte7-6 lists "onn""t"O

itre tiiiei components

in thEcircuitfor eachof the six OanOwiOttrsData. bits 2, 1: "1! 4 are apptiedto switch U2O15B(pi-nsB, 16, and 9) which selectsthe components. frorir U2OOOB,the signal is routed through contacts Z ana 6 of switch !9.qpp to.edgeconnectorpin 57 as th€ VtoEOFILTER OUTsignal.

Video Blanking

The video btankingcircuits allow selectiveblanking 9l_!h" lower and upper ends of the locat osciilator range. Selectiveblankingis requiredbecausethe local oscillatgrsw€epsthe fuli span-regardless

ot the band

s_y:temis desisn;cto op"n IT,r-.:,].P.,:9:?

a.otsptaywindowonly duringthe time "tr""tiu"ry for-*iiro"orput"r,display. Data

bits 5, 6, and 7, under coritrol of the

selectthe appropriateamosntof displayfor eacnend.

Video blankingand the PRESELECTOR

.DRTVEsig_ nal (which providesfrequencyinformation,in voltag-e rorm) are located on the ViOeo processor board. ::1,:h_ yg.0g3.incorporates a disabte function rhat, wnen provicteda tow input, opens all switch s€ctions regardless of individualsection input. This feature allows the VTDEOFTLTEROUT signat to be easity blankedat wiil.

The disablefunctionis controlledby a combination of outputs from comparators U30154 anO UgolsB. I11ttlq.these comparatorsare from the PRESELEC_ TOR.DRIVEsignaland a combinationof vottagedivid- ers that are switchselectedundercontrolof dai=abits 5, 5, and 7. The PRESELECT_OR

DRTVEsignatis applied from edge connectorpin 54 through OiiiJer resistors R4013and R4012to the invertingiriputoi UgOtSR,anO throughdividerresistorsR4014inO'Ra0tito the non_ invertinginput of U3O15B.These dividersrectucethe excursionof the drivE.signalfrom (+10V to _10V) to (2.5V to -2.SV), which is the maxlmuminput tevetto the comparators.

Input to the non-invertinginput of U3015Ais from dividerresistorsR9011,RgOld and selectedr€sistor R4015. The inctusionof R4015is controltedby DB7 throughpins 2 and 3 of U9025. The junctionof divider resistorsR3011and Rg0l2 is connectedto ground throughR401Sfor band2.

Inputto the invertinginputof Ug0158 is fromdivider resistorsR4018,R4012,and selectedresistorRgO2g. The inclusionof 83023 is controlleOOy OeOthrough pins 10 and tl of U3025. The junctionoi Rg0t anO R3012is connectedto +S V ttrr6ugnRO0rSwhen it is selected.This switchingarrangementof negativeand positive levels for comparisbn with the reduced PRESELECTORDRIVEsignatenabtesthe iop and bot_

Theory of Operation- 494Al4g4ApService,Vot.i

tom extr€mesof the frequencyexcursionto be blanked. The blankingis activatedby the disable function of switch U3063, which is controlledby the microcom- puter.

DlclTAL STORAGE(Diagrams25 and 26)

The Digitat Storage circuits provide the abitity to store and process a signal before displayingit. fnis allows flicker-freedisplays,Even at tire'stowswesp rates required for narrow resolution bandwidth meaj- urements.Digitizingthe signalalso allows signalpro- cessingand markergeneration.

.--Th-"processingincludesdetectingpeak amplitudes (Max.Hold),storing a signat(SaveA),'subtractingone signal from another (B-Save A), signal averiging (Averaging),and signal comparison(View A anOVei g)t These operations use two memory banks to independentlystore two completesignalstirat are Each digitizedat 500 points across the lweep. Therefore, two signals may be observedsimultaneoustyor pro- cessedin separateways.

The markers are used in a variety of ways. There ar€ two waveform markers that th€ user sets for vari- ous measurements. In addition, an update mad<er showswhere the actualsweepis with reierenceto the refresheddisplay.l

Four instrumentbus addressesare associatgdwith Digital Storage. Addresses 7A and lB are write addresses.FA and FB are read. Theseaddressesare shared by both the Horizontal and Vertical Digital Storage circuits. Logic on the Horizontal Oilitat Storage board controls which set is activo. 7A onlne HorizontalDigital Storagaboard is further subdivideO into I subaddressesby 3 bits in address ZB on that board. Addresstablesin the circuitdescriptionsfor the appropriateboards show detailsof the DigitalStorage addresses

In the Max Hold mode, the highest amplitudeat eachof the 1000 pointsin successivesweepsis stored and displayed.ln the SaveA mod€,a signalis storedin one memoryfor later examination,and is not updated. In the B-SaveA mode,the A signalis stored and not updated,then arithmeticailysubtractedfrom the B sig_ nal, which is stored, but continuallyupdated.tn ttre averagingmode, the displayarea is dividedby a hor_ izontal cursor. Signals above the cursor are peak cletect€dand displayed,and signalsbelow the curcor are averaged.ln the View A and View B modes,the contents of the selected memory or memories are displayed.

_89t9_are als"-rid* rnarkers lhat may be fed to the ,ear-panel MA8KER I VIDEO input These video mdrkers are from an exliernal source, and are not part of the digital storage system. See the vroeo processor description for more informaiion about the video matkers.

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