Tektronix 494AP service manual O o, O a o O a o o o o o o

Theoryof Operation- 4g4[l4g4Ap Servlce,Vot.1

ROM.The ROMin this instrumentis locatedon this boardand on th€ ROMBanks& GptB board(A56).The ROMconsistsof systemROMcontainingthe instrument operatingsystemand the programRoM containingthe variousmeasurementsroutinesand crt messages.The system ROM is alwaysaccessible,while the program ROM is bank switchedas necessary. Bank switching allows expanded memory within a limited address space. The systemROMand part of the bank-switched ROM are locatedon this board. The remainingbank- switched ROM and the p6n1 switching circuitry are locatedon the GPBboard(A56).

The ROM lCs are 32K-by-Bbit erasableprogram- mable read-only-memorieswith fifteen addrees lines ancleight data lines. Each contain32K bytes of data. Normally,the ROMsare not erasedor re-piogrammed.

U3050 includesthe system ROM and one bank of th€ bank-switchedROM. The ROM frorn C000-FFFFis the system ROM, always accessiblefrom any ol the bank ROMs. The ROM from 8000-FFFFis a ROM bank. U2040Cand U2040Dailow both the g0O0and C000 addressselectionlines from LJ2O4Sto selectthe same physicalROM. The two halves are selectedby address bit A14. For addressesC000-FFFF,A14 i; high. This address range is also enabled through U3030Cand U3030D.

For the bank addrEsses,9000-BFFF,A14 is low. Data bit D4 must be high when stored at the bank sefect address, 7E00. by tatch U4020. This enables U3050throughU3030D.

U3060 comprisesROM banks 0 and 1. This lC is :?le_cleq_lvhenthe processor addresses the range 8000-BFFFand when the CEOsignat from the GptB board (A56)is active(low). Selectionbetweenbanks0 g."q1 is done by the bank.selectbit latchedfrom D0 by U4420. This latchis enabtedwhen the BANKsignat(ai address7E00)goestow fromthe GptB OoarO

1A56).

ROM Banks and GPB (Diagram 43)

The GPIB board (A56) contains most of the instrument'sbank-switch€dROM and the Generalpur- pose InterfaceBus (GPIB)circuits. The GptB Interface boarcl{A30A5f connectsthe instrumentto the GptB (IEEEStd 488 bus). On the non-programmabteversionof the instrurnent,this output is only used to drive a plotter.

'Address Decoder.DecoderU1O5S,gatedby the d2 Clock, is addressedat 7800 by the t/O line from the Memory board (A54). Address lines Ag-A10 produce enablesignalsfor startingaddressesas follows:

7-96

7400for the 9914AGPIA

7C00for th€ GPIBSwitchDataBuffer 7E00for the ROMBank SelectEnable

Bank Selector. Bank switching expands the addressing capabilitiesof the microcomputer. The BankSelectorcircuitallowsaddressing272Kof ROMin seventeen16K banks. Each ROM lC holdstwo banks in its 32K bytes of memory. Banks 0, 1, and 16 are located on th€ Memory board (A54). Banks 2 through 15 are locatedon this board.

Latch u2044 reads th€ data bus at address 7E00. 8it D4 selectsbetweenthe first sixt€enROMbanksand th6 seventeenthROM bank (located on the Memory board). When high, bit D4 enables U3050 on the Memoryboard(A54). Whenlow, bit D4 enabtesU1O40 on this board.

When the lower ROM banks are selected,bit D0 selects even and odd banks by driving the most significantaddressline on each ROM lC. When D0 is low, the lower addressesin each ROM are selected. These are the even bank numbers. When D0 is high. the upper(oddbank)addressesare selected.

Bits Dl throughD4 drive decoder U1040. Bit D4 enablesthe decoder,and bits Dl throughD3 provide the chip enablesignalsfor the ROMs. Whena bankis selectEd,it is addressedin the 8000 through BFFF range. lf anotherbank is selected,new data is written to the Bank Selector.Table 7-23 lists the ROM set€c- tion datafor the lowersixteenbanks.

The light-emitting-diodes(LEDs) on U1040'schip enable outputs are diagnostic indacators.When the instrumentis placed in a self-diagnosticmode, the LEDs signalresultsof the tests. See the Maintenance sectionfor furtherinformation.

Bank ROMs.The bank ROMs containmosl of the firmware. This includesfunctionssuch as controlpro- grarns,rneasurementroutines,and crt messages{with alternatelanguagesif installed).

The memory lCs are 27256 32K-by-8 bit erasable programmableROMs. They each have 15 address

lines,I data lines,a chipenableline,an outputenable line, and a programvoltageline. Normally,the ROMs will not be erasedor re-programmed.

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