Tektronix 494AP service manual C o o o O o o o o, O o o o o a o, AddressBusTest

Maintenance- 494A/494ApService Vot. 1

!.A" microcomput€rnext tests U2015,a timerchip on th€ Procassorboard. lf any of the timers in U201b result in timo d€lays that ar€ too short or too long, the test stopswith LEDDS10Sgon th€ GptB boardtit.

6.The microcomputerresets the GplA, U2050,on the GPIB board and checksto see that the GptAis not addressedto talk or listen. The GplA is set to the listen-only mode and checked to see that it is addressedto listen. The GplA is then set to the talk_ only mode and checked to sEe that it is addressedto talk. lf any part of this step falls, the test stops and LED DSl052 on the GPIBboard is ilt.

lf all steps in the test arE successfullycompletEd, the microcomputer lights LED DS10S4on the GptB board. The LED is lit continuouslyif no empty ROM sockets are found, or putsed the number of times correspondingto the number of empty RoM sockets found. lf the number of pulses is greater than the number of absent ROMs, a ROM (or ROMs) was missed in step 4. Look tor a problem on the chip-s€lect line or on the D7 databus line.

lf th€ microcomput€rsystem passes the t€st, but does not controlthe instrum€flt,run the lnstrumentBus Checkdescrib€dtaterin this section.

AddressBusTest

Select the address bus t€st by moving jumper P3015 on the Processor board to th€ TEST position. This forces the microprocessor(U1025)data linss to hexadecimal5F. As a result, the microproc€ssorcon- tinuouslyexecutes a CLR B instruction,and rep€titively cycles throughall of itE address space.Thereshouldbi

aknown pattern on the microcomputer address and control lines and at th€ output of th€ addressdecoders. This allows qualified servic personnel to corr€ct prob-

l€ms that pr€vont the microcomputerfrom running its self-t€st.

The spectrumanalyzerwill not functionwhile run- ningthis test.

Mlerocomputer Bus As the microcomputer cycles throughits address spac€, it togglesthe address lines. The MSB, A15, has a period of approximately 1540ms. Eachline, 414 through A0, has a periodhaif that of the previousline.Thus,the LSB A0 has a period of approximately4.7 ps. High-orderlines A15 through A12 ara shownin Figure 6€2. lgnore the narrowpulses that may be evident during the low portion of each cycle.

6-52

Figure6-32.A15throughA12ln mlcrocomputortestnode.

The data lines on the microprocessorside of U2025 on the Processorboard are static; D7 and D5 are low, the oth€rs are high. The TEST positionof P3015dis- ables U2025.On the bus eidE of this buffer, the data lines are driven by the various memory devices on the bus as theyare addressed.

Examlnlngthe data lines can locate shortedor open lines; i.e., lines inactiveat hlgh, low, or in-between states or changingin unison,usuallyto indeterminate logic lev€tsof +1 V to +2 V. A problemr€lated to a par- ticular device may be evident only while that device is addressed.

Memory Address Decoders - Address decoder U2045on the Memoryboard sets its outputs low in turn to access blocks of memory space. The four main block-selectorrtputsare shownin Figure6-33.

U3025 on the Memory board decodes the RAM addresses. Becauseof the power-upconditlonof the bank select,only one of the non-volatileRAM chipswill be selected.The RAM seleotoutputsandtheir relation- ship to 6-ffi andl{ffi are shown in Figure 6€4 and Figure6-35.

U3040and U3045on the Memoryboarddecodethe T/O-selectlineandth€ selectlinefor S1050. Thesesig- nalsare shownin Figure6€6.

lgnore the narrow pulses evidentduring the time eachoutputis asserted.The pulsesresultfrom address linestogglingbetweenmicrocomputercycles.

a o o

t

Io

o

I

o

I

I

Io

o o o o o o o a o

I

o o

I

a o o

I

o a c o o o

O

e o o o o o o