Tektronix 494AP service manual O o o o o

Theory of Operation- 494A1494ApService,Vot. 1

combinationwith multiptexerU2020,supptiesthe CON- STANT data to U2030. MuttiptexerU2A2Ois, in turn, controlledby addressbits 0, 1, and 2 to providethe proper constantdata bit to u2030.

Output Clrcults. From the U2030 verticatdisplay register, the parallel data output is applied to 6-Oitdigital-to-analogconverterU1035.The convefteroutput is then applied to the output storage/cursorswitch, U20408,througha vectorgeneratorthat consistsof an integrator(Ul040 and Cl03S)with an associatedfeed- back loop sample-and-hotdcircuit.IntegratorUl040 has

atime constant that provides a ramp to tast between the existing sampl€ and the new sample (that is, betweensyncpulses).

Circuits U2M0A and U2045 and capacitorC204S make up a sample-and-holdcircuitwith U2045actingas an output buffer. From U2045, the output current through resistor R1036 subtracts from the digitat-to- analog converter output current to modify the slop€ of the output ramp. The output of the vector g€nerator is then appliedto switch U20408.U20408,controltedby the MKR (marker)signal from the horizontalsection, selectsbetweenthe recreatedvideo signalfrom u1040 and a dc (Peak/Average)levelfrom buffer U304S,to be sent out as the v€rticalsignat.The dc levelis displayed only during rotraceas the PEAK/AVEBAGEcursor.

Peak/Average Level Circults. The buffered PEAK/AVG LEVEL signal, from U3045, is compared with the sampledVideo FitterOut signat,from U1045, by comparator u2035A.The output of u2035Ais a high

(1)if the video Fitter out signal is greater than the PEAK/AVGLEVEL,or tow if it is tess. This output com- mands U2030,via U4040Cand U4040D,to send peak or averagedata to the output.U40408,C, and D are

used if the instrumentis underGPIB controlto select one of three possiblemodes;peak, Average,or front panelcontrol knob.

Horizontal Section (Diagram26)

Figure 7-16 is a block diagram for the Horizontal ControllC U5020.The horizontalanalogvottageis con- vertedto a currenttablevaluethrougha 1O-bittracking analog-to-digitalconverter (adc), which consists of up/down interlock and 1O-bit up/down counter in U5020, and external10-bit digital-to-analogconverter (clac)U4040.

7-44

As the sweep movss right, the counterIncrements; as the sweep retraces. the counter decrements.Each time the counterincrements,it generatesa new X coor- dinate value (the dac input) and a ST DIV (start ctivide) signal to start the storage cycle. The incrementclock is the SYNCsignal,and th€ decrementclock is the basic digital storageclock dividedby two. Whenthe SaveA mode is selected,the counter skips everyother binary nUmber,so only B coordinatesappsaras addresses.

Astate machine provides the horizontal syst€m intelligence.This circuitdetermineswhichtraceto write on the screen,determineswhen to switch from read to write, generatesthe B-A coordinationsignalsfor verti-

cal control lC (on th€ Vsrtical Digital Storage board), controls the g-bitdisplay counter incrementing,and proc€ssesrequestsfor the memorybus.

Whenan externaldevice€lectsto readfrom or write to m€mory,it allowsthe BUs REQ(busr€quest)signal to go high to request permission from the state machine.When the time becomesavailable,the state machinepullsthe BUS REQline low, which signalsthe start of a requestcycle,For the next eightclock cycles, the internal multlpl€xer output lines are in th6 high- impedance(open)tri-statsmodE.

The combinationof the up/down interlock, 10-bit up/down regist€r,9-bit display counter,and horizontal display multipl€xerconstitutethg primarycircuits that either write to or read from m€mory. To generate X values to be written into memory, the circuits convert the sweep voltageto binary form. Thesecircuitsalso count the sync cycles to cause the external logic to read stored data from m€mory and produce a vertical signal(Y value)for eachcorrespondingX value.

During acquisition cycles, the 10-bit up/down counter,controlledby the up/down interloclqoperates in a loop with the external10-bit digital-to-analogcon- verter. Thisallowsthe counterto acquirethe equivalent (X value) of a sample section of the sw€ep voltag€. Fromthe counter,the 10-bitoutputis appliedto the 10- bit up/down register. During display cycles.the g-bitdisplay counter counts sync pulses to acquire the x value. Eitherthe 1o-bit up/down registeroutput or the displayregisteroutputis appliedto the horizontalmulti- plexer under control of the SELECTsignal from the State Machine. From the multiplex€r,th€ output is appliedto ths m€morlesas an address.

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