Tektronix 494AP service manual O e o o o o o o o o o o o, O o o a, O o o o o e

Theory of Operaton - 4g4[l4g4Ap Service,Vol. 1

The Synthesizercan be dividedinto threefunctional blocks: the 100MHz divider,the SOMHz divider,and the -+Ncounter.

The 100MHz divider consists of flip-flop UgOgOA and transistorsQ3040and e3041. The 100MHz signal from the 3rd Converterstags is appliedto the clock input of u3030A. u30308 furnishes a stable bias sourcefor the U3030Aclock input. The signalfrom pin

3of U3030Ais apptiedthroughO3O4Oto UtO+Og,ine

50MHz divider. The 50 MHz signaltrom the e output

is appliedthroughbufferamplifiere3041 to PSOO {not

used in this instrument).The two transistorsprovide ECLto TTLlevelshifting.

The 50 MHz dividerconsistsof the flip-flopU10408.The 5OMHz signatfrom e3040 drivesthe ctockinputof Ul0408, which dividesthe signatto 25 MHz. The sig_ nal from th€ Q output is sent to the Offset Mixer cir_ cuits. The complementsignal is apptied to the +N counter.

The r-Ncounter consists of shift regist€r/latch€s U2020and U2030;countersU2010,U1O2O,and U1030; and flip-flopU1040A.The circuitis controiledby three signalsfrom the microcomputervia the Counterboard. The output of the +N counter is the +N fr€quency, which is appliedto the phase/frequency

detectorin the

OffsetMixer.

The threecountersconnectto form a 12-bitcounter, overflowlngafter a count of 4095. When phase lock operationis selected,the microcomputersends serial data and a dataclockto load a numberintothe latches. The numberrangesfrom 3300 to ggg0, so the count remaininguntil the counters overflowis from 265 to

795.The 25 MHz counterclock is dividedby the count remainingto producethe +N frequency. At power-up

and other timeswhen not phaselocked,the counteris allowedto countto 4095for a 6 kHzoutput.

When the numberis loaded,the N LATCH signat transfersthe numberfrom the input shift registersto the output latchesot u202Qand U2030,presertingthe count€rs. Onceloaded,the counterscountat a 25 MHz rate to accumulatethe remainingnumberof digits until they are full. The carry output of U1030(pin 15) then moves high and U1040Achangesstate. This reloads the counterstageswitha new numberfor anothercount cycle. The carry output of U1030is again simultane_ ously set low so the next cycle of the 25 MHz signal clocksUl040Abackto th€ resetcondition.

The outputof U1040Ais a seriesof posltivepulses that range in period from 10ps to 31 &s which is equivalentto 94 kHz to 32 kHz. This signatis sent to

7-84

the phase/frequencyd€tector in the Offset Mixer for comparisonwith th€ difisrencefrequencygeneratedin the mixercircuit.

Phase Lock (Diagram 40)

The PhaseLock circuitslock the lst LO, usingthe Synthesizeras a reterence.The circuitsshownon this diagram include the Ofiset Mixer (A50A3, Error Amplifier (A50A4), Controlled Osciilator (A50AS),and StrobeDriver(A50A2).The lst LO (A16)andthe Phase Gate Detector (A24) are also maior parts of the phase lock circuitry.

Offset Mixer. The Offset Mixer (A50A3)circuitsmix the synthesizerand VCO outputsand comparephase and frequencywith th€ divid€-by-Nfrequencyfrom the synthesizer.The resultingerror signaldrivesthe inner loop amplifieron the ErrorAmplifierboard(A50A4).

The circuitsconsistof a ringdiodemixer,differential amplifier,and phase/frequencydetector. For this expla- nation.assumethat the ControlledOscillator(VCO)fre- quencyis at 25.06MHz and the +N signal is 50 kHz. The 25.06MHz signalfrom the VGOentersthe boardat pin N of the OffsetMixer assembly. The signaldrives the base of transistor Q2021which drives transformer T2010. The transformeroutput connects across the ring diode mixer. The 25 MHz referencefrequencyis applied at pin K of the Offset Mixer and coupled through T1010 to the ring diode mixer. The four fre- quencycomponentsare pickedofr at th€ cent€rtap of T2010.A low-passfilter pass€s the 60 kHz difrerence frequencyand blocksthe two fundamentalfrequencies andtheirsum.

TransformerT2030 couples the 60 kHz signal to differential pair Q1020 and 01030. Then Ql040 amplitiesthe signalto TTL levelsand appliesit to the clock input of flip-flop U10508, part of the phase/frequencydetector.

The phase/frequencydetectorconsistsof flip-flops Ul050A and U10508,NANDgate U20508,and inverter U2050A. Now, if the loop had bEen locked,the two flip-flop clock input signals would have been edge- coincident. Pin 4 and 5 inputsof U20508would have moved high and after the signal at TP1058goes low, the NAND gate would have reset both flip-flops. This results in a series of pulses of equal amplitudeand width from each of the flip-nopswhich,when appliedto the Error Amplifier,wouldnot shift the frequencyof the

vco.

However, in this example the +N signal is 50 kHz and the difference frequency from Q1040 is 60 kHz. Thus, Ql 040'soutput leads the +N signal. In this case,

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