Tektronix 494AP service manual A o a o A a o o o o a o o o o o O o o o o O a A o o o o o o

Theoryof Operatlon- 4g4A/4g4ApService,Vol. 1

Sweep Holdofr

During retrac€, the sweep must b€ held off long enoughfor the timing capacitorsin the integratorto dischargeand the circuitto stabilize.To preventflicker, the holdotfperiod must vary as sweeptim€ changes. U30258and threetimingcapacitors(C3027,C3030,Lnd C3032)plusa resistor(R3030)formthe hotdoffcircuit.

Duringsweep time pin 5 of U1017Ais high.This pulls pin 6 low and dischargesCg0g2. Duringretrace, pin 6 is released and the timing capacitorsstart to charge. When they reach *5 V comparator Ug025B togglesand its output goes high. This, along with th€ high on pin 13 of the NANDgate U102OD,providesthe clock pulsefor U2026to pass a trigger signatthrough to the Sweepstate controt,u1025.

lnterface Circuits

ln additionto the sweep circuits,there are circuits that interface between the microcomputerand the ReferenceLock modul€. These circuits generate an interrupt(SER REO) when a change of status in the ReferenceLock moduteoccurstrespondto the POLL routine, and provide data so the microcomputercan monitorthe statusof the RelerenceLockmodule.

To determine the status of the ReferenceLock module,the microcomput€rreads the status of bits 0 and 1 (DBo & DBl) of the data bus at address 9F. These two bits connect through tri-state buffers in u4015C to th€ NTL REF and (REF LOCK)(bar)tines from the R€f€renceLock module. The INTLREFline is high when the internalrEferenceis used and low for extemal referenc€. The {REF LocK}(bar) goes high when the 3rd LO is not locked to the frequencyrefer- enceand low whenit is locked.

When address 9F is read, U2O1Zis enabledand latches the (NTL REF)(bar)and REF LOCK signals. Thus,the bits on pins 1,2,and 5,6,of the exclusive-nor gates in U2015match each other. The open-collector outputs are wired together,so when the outputs are high,inverterU10178appliesa lowto the clockinputof flip-flopU2025A. Whena changein statusoccurs,one of the bits to the exclusive-norgates (pin 1 or pin 5) changes.Thereis now a difrerencebetweenthe present status and the previousstatus,stored in U2017. One output of U2015 now switcheslow and a low-to-high transitionoccurs on the clock pin of U2025A. This triggers an interruptand causesthe microcomputerto inquireabout the new status. Readingthe new status activatesthe latch and resets the circuit. Transistor Q3015,drivenby bit D4 at address1F, turnsthe INTL REF(internalreference)on or off.

7-64

The Interruptand ServiceRequestcircuitgensrat€s the instrumentbus interruptsand respondsto the sub- s€quent poll routine from the microcomputer.Thereare two sources of an interrupt from the sweep board, either an EOS (end-of- sweep) has occurr€d or a change of status of the reference lock module is detect€d. Whenan EOSoccurs,and provldedthe EOS Interrupt Enable bit is high, the flip-flop U1010Ais clocked and its Q(bar)goes low. This producesa high out of u1020Bwhichturns Q4032on to pullthe instru- ment bus line SER REQ (servic€ request)low and forcesan interrupt.

The microcomputerresponseto an interruptis with a poll routine, lt first writes FF to the instrument address bus. The Sweep board addressdecodersnor- mallyr€spondonlyto addresses0F, lF, and9F,but the interruptcircuit detects when bit 7 of the addressbus (AB7) goes high. The microcomputerrais€s the POLL line and reads the instrumentdata bus. The outputof U2010A goes low. This. anded with the low out of U10104,generatesa high to turn 03020 on and pullbit DB4 of the instrumentbus low. When the microcom- puter reads a low on bit DB4 it lowersthe POLLline and writes 7F on the instrum€ntbus. Again,none of the otherdecodersrespond.However,bit 7 (AB7)of the addressis pulledlow. The microcomputernowwritesa word to the data bus with all bits sxcept bit DB4 high. This acknowledges the interrupt. The microcomputor

now raisesthe POLLline againand sincebothinputsto U20108are high,the outputof the gategoes low. The POLL line is then pulledlow and the low-to-hightransi- tion clocksthe low on the D inputof U10108throughto resetu1010A. lts Q outputthen setsu10108. 04032 is cut off, the interruptis removed,and the circuit is now readyfor anotherEOS.

Achange-of-statusin the referencelock module causes a low-to-hightransitionon the clock input of u2025A to latch the Q (pin 5) output high and the o(bar) output low. This low is gated throughU10208to turn 04032 on, and pull SERREQline low. Whenthe micro- computerresponds,by writingFF and raisingthe POLL line, U2010Aoutput goes low, however,at this time U202OBoutputgoes high,becauseof the low on pin 6 of U2025A. This turns 03025 on and bit DB7 on the instrumentbus goes low. The microcomputerreads this and pullsthe POLL line low. Address7F is written on the addressbus and the POLL line is raised. This lorces U2010Bto outputa low and th€ POLLlineagain goes low to toggle U20258. The low Q outputresets U2025Ato removeth€ interruptor SER REQ. At the same time U2O25Bis reset and the circuit is readyto repeatthe sequence.

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