Tektronix 494AP service manual A o A a o, O o a o o o o o

Theory of Operation- 494Al4g4ApService,Vol. 1

lf the PwR FAIL line returnsto a high state beforethe microprocessoris reset, the microprocessordoes a power-upinitializationto ensure that the instrument operationwill not be affectedby a temporarypower loss.

This powerfail sequencecan be disabledby remov- ing jumperW2035. This may preventlalse resetswhen operating the instrumenton noisy power. However, power-downsettingswill not be stored.

Memory (Diagram 42)

The M€moryboard(A54)containssomeof the ROM

and all of the RAM usedby the microprocessor.There are 64Kr bytesof ROM in two g2K byte EpROMsand 32K bytes of RAM in four 8K byte RAMs. Battery backup power is suppliedfor 16K of the RAM. The board also contains the Options switch, which sets some instrumentoperationsand selectsprocessortest modes. AdditionalROM is locatedon the GplB board (As6),

Address Decoders. The addressdecodingcircuits rnonitorthe microcomputerbusto enablecircuitson the board. DecoderU2045is the main addressdecoder, selectingfour 16K-byteblocksof addressspace:

0000€FFFfor RAM

4000-7FFFfor NVRAMand t/O

8000-BFFFfor BankROM

C000-FFFFfor systemROM

The upperhalf of U2045decodesthe non-volatileRAM and l/O space. The lower half decodes th€ system RAM and the ROM space. The OZClocksignalctocks the lower half of U2045to assureproper memorytim- ing.

The systemRAM addressspace is the 16K bytes from 0000€FFF. The 2K space from 7000-77FFis switched b€tween eight 2K banks of the 16K non- volatileRAM.

The systemRAM addressspaceis dividedbetween two 8K RAMs,U101Oand U3020. The lower half of U2045, U3030C,and U3030DenabteU1010for the addressspacebetween0000and 1FFF. The lowerhalf of U2045 and the upper half of U3025 decode addressesfrom2000€FFF. This enablesU3020.

The non-volatileRAM is bank switchedinto eight2K banksaddressedfrom 7000throughTTFF.Thisallows more rnemorythanthe processorcan directlyaddress. At address7E00,the bank selectcircuiton the GplB board (456)enablestatch U4020. The tatchhotdsthe

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7-94

RAM bank number from bits D+D7 of the microcom- puterdatabus.

LatchEdbit D7. tne 62 andthe 7000addressenable from the upper half of decoderU3025drive the lower haff of U3025for the 7OA0-77FFaddr€ssspace. lf D7 is low,U1030is enablEd;if hlgh,Ul020 is enabled.The othertwo bank selectbits,D5and D6,directlydrivetwo address lines, creating four banks in each of the 8K RAMs.

The l/O space is decoded by the upper half of U2045,U3040,and U3045. The upper half of U2045 enablesU3040for addressesfrom 7000-7FFF.U3040 then decodesthe 7800-7FFFaddresstor Optionscircuit and other l/O space. This llne is sent off the board as the l/O signal. The Options circuit is addressedat 7800 by U3045.

ROM address decodingis performedby the lower half of U2045,data bit D4, some gates, and the bank select circuits on the GPIB board (A56). Half of ROM U3050is addressedas bank ROM from address8000 through7FFF. The other halfof U3050is systernROM addressed at C000 through FFFF. The bank ROM address space is shared with 16 other ROM banks.

Latch U4020 stores data bit D4 at address 7E00 {Bank enable). When that bit is high, and when ths ROM

banks are addressed,U3050is selected. The latched bit enablesU3050throughU3030D. For systemROM addresses, thg CXXX enable through U3030C and U3030D,and through U2040Cand U2040D enables u3050.

U3060is selectedas banks 0 and 1 by the bank selectcircuiton the ROMBanksand GPIBboard(A56).

The upperand lower addressesare selectedby data bit D0 latch€d by uao20 at address7E00.

RAM. The RAM is dividedinto systernRAM and non-volatileRAM. The microcomputeruses the system RAM for interim data storagewhile the instrumentis operatang.The non-volatileRAM stores changeable data suchas waveforms,readouts,and front-panelset- ups. The non-volatiledata is backed up by battery powerwhenthe instrumentis not operating.

U1010 and U3020 form th€ main system RAM. EachlC contains8K bytes of RAM, making16K bytes

totalsystemRAM.

U1020and U1030form the battery-backed-upnon' volatileRAM. When the instrumentis operating,these RAMs are powered by the +5 volt supply. When the instrumentis not operating,the RAMs are poweredby

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