Tektronix 494AP service manual

Theoryof Operation- 494A/4g4ApService,Vol. 1

Clock. This circuit generatesthe clock signatthat drivesthe microprocessor,the GplA transceivdron the GPIBboard(A56),and the charactergeneratorcircuitry on the CRTReadoutboard(A66A1).

Y1030,Q2035,and e1030 form a clock circuitthat oscillatesat 3.4133 MHz. e2095 and y1030 form a Colpittsoscillatorand el030 buffersthe output,giving

aTTL compatibtectock signat. This signatis turtnei bufferedby U2030Aformingth€ crt clocksignat.

Mlcrocomputer Bus. Microcomputercommunica- tion with memoryand l/O is via the microcomputerbus. The bus consists of eight data tines (D0-Dti),sixteenaddresslines(A0-A15),the RESETtine,the VMA(Vatid MemoryAddress)tine. the Read/Write(R/W)tine,and the 62 Clock.

The data lines connect from the microprocessor through bi-directionalbuffer VZ02S. The Read/Write line controls data directionthrough the buffer, When the microprocessorreleasesthe addressbus, the Bus Availableline(BA)disablesthe databus buffersthrough U3036A. Jumper P3015 is a test jumper that ailows disablingthe data buffer and forcing a CLR B instruc- tion to the microprocessor. Diodes CR2O20and CR2025pull data tines MDS and MD7 tow, issuingthe CLRB instruction.

The addresslines connectfrom the microprocessor through buffersU3030 and U302S. These buffersare disabled when the DMA Controller is granted the addressbus. Thenthe addressescome from the DMA Controller,U1020,throughDMA addressbuffersU1015 and U1024. U1015is a bi-directionatbufier,allowing the microprocessorto addressthe DMAControiler.

The RESETsignalis a functionof the powerFailure circuit. Whena powerfailureis sensed,the RESETsig_ nal resetsthe Timer, PlA, DMA Controlterand. circuits on the Memory (A54) and cptB (A56) boards, The PowerFailcircuitis discussedin moredetaillater. The VMA, R/W, and 02 Ctock signats have atreadybeen described.

Address Decoder. AU303Sdecodesthe addresses for the l/O circuitson this board. Whenthe micropro- cessor selectsan address in the range of 7g00-7FFF. the l/O line from the Memory board (A54)goes low, enabling U3035. The decoder then subdividesthe address range to select each circuit. Figure 7-3.1 showsthe UOaddressmap. Eachcircuitusesonlyone or a lew addresseswithinits range.

Tlmer. The Timercircuit,U2015,is a 6840program- mable timer used by the microprocessorto generate variabletime delays. The processorprogramsan inter- val into the timer. Whenthe intervalpasses,the Timer generatesan interruptfl-imerSRA). The {2 Clocksyn- chronizes the Timer with the microprocessor. An addressin the timer rangeselectsthe Timer. Address bits A0-A2selectinternalTimerregisters,count€rs,and latches. When the ReadfAlrite (RfA/) line is low, the Timer acceptsdata inputfrom the data bus. Whenthe line is high, the Timer puts its data on the data bus. See a 6840data sheettor additionaldetails. The Timer addressingis mappedin Figure7€2.

PIA and InstrumentBue. The microcomputercom- municateswith the instrumentthrough the lnstrument Bus.The6821PlA,U1010,interfacesthe DigitalControl circuitsto the InstrumentBus. This bus containseight data lines (DBO-DB7),eight address lines (AB0-A84, the DATAVALIDline,the ServiceRequest(SERREQor SR)line,andthe POLLline,allthroughthe PlA.

The PIA receivesRead/'li/rite,02 Clock, and RESET control signalsfrom the microprocessor.Figure7-32 showsthe PIA addressmap.

The addresslines are bufferedby U3015. The data lines are bufferedby bi-directionalbuffer U3010. The buffer is gated on when data is valid. The most significantaddressbit selectsdatadirectionso that half of the addressspace is for writing to the instrument, and half is for readingfrom the instrument. The PIA CB2 port(U1010pin 19)goeslow whenthe dataon the lnstrument Bus is valid. Resistor-capacitorcircuits delay the DATA VALID signal to the InstrumentBus. assuringthe proper timing relationshipwith the other InstrumentBus signals.

The PIA issuesthe POLL and DATA VALIO(or DV) signals in response to a service request from the hardwareon the InstrumentBus. The requestingcircuit respondsto the POLL signal on the InstrumentData Bus.

The InternalControl(INTLCONT)signalcomesfrom the AccessoriesInterfaceassembly(A30A76).This sig- nal is normallyhigh unlessexternalcontrol throughthe ACCESSORIESconnectoris desired. When low, the Bus Enablesignalgoes high,disablingthe addressand data buffersand the DATA VALID and POLL outputs. The Bus Enablejumper,P3010,may be removedto dis- ablethe InstrumentBus for test purposes.

DMAController.Whenthe instrumenttransfersdata throughthe GPIBinterface,the DMAController,Ul020, sets up direct transfersbetweensystem RAM and the

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