Tektronix 494AP service manual

Theory of Operation- 4g4Ll4g4ApServlce,Vot. 1

As eachnew Y valueis converted.it is addedto the eight least significantbits of th€ numerator.Eachcarry from the most significantbit of this additionis counted by a 17-bitripplecounter.The contentsof this counter and the 8-bit sum are cascadedto form a 25-bitgrand total. Eachtime a new sampleis addedto the numera- tor, another17-bitripplecounteris incrementedto pro- ducethe denominator.

Adivisioncyclestartswhenthe horizontalcontrollC (on the HorizontalDigital storage board) detects a changein ths x value.At that tim€ it generatesth€ sT DIV(startdivide)signal. On receivingthis signal,and in synchronizationwith the SYNC signal,verticatcontrol lC U2030doesfivethings(referto Figure 7-15):

1.Latch€s the current numeratorin a 25-bit latch

(25-to-1data concentrator)and latchesthe denomi- natorin a 17-bitlatch(17-to-1dataconcentrator).

2.Clearsthe numeratoradder circuits(25-bitsum- mationregister).

3.Performsa 17-bitpriorityencodeon the denomi- nator and loads a 1 in the appropriatecell of the 25-bitshiftregister.

4.Loads the latched nurneratorand d€nominator seriallyinto the dividecircuit (subtractor)usingthe contentsof the 25-bitshift registeras a mask.

5.Clears the denominatorripple counter (1Z-bit counter)to zero.

Ten clock periodsare requiredto load the numera- tor and denominatorinto the divide circuit.The cycle starts on a SYNCpulse.The lirst bit of the quotientis availableshortly aft€r the first clock pulse that follows the next SYNCpulse.Divisionis performedby repeated subtractand shift operationsTh. € quotientis arrivedat seriallywith the mostsignificantbit first. Sinceontyg-bit accuracyis required,with the priority encoderoutput used as a mask,the dividercircuitis loadedwith the g most significantbits of the denominatorand the 16 most significantbits of the numerator.(Rippleborrow for a 17-bitby 25-bitsubtractorwoutdbe so tongthat it wouldbe impractical.)

The peak circuitconsistsof a peakdetectorand an 8-bit peak shift register.In operation,the previouspeak

Yvaluefrom the last set of samplesis still storedin the peak shift registerat the start of a conversioncycle.At that time, the peak detector,which is a serialcompare circuit,is set to the statethat qu€stionswhetherthe old or new numberis larger.Each bit of the new value is then comparedwith the correspondingbit of the old value,most significantbit first. Whenone valueis found to be larger,a flipJlopis set and the smallernumberis gatedout of the shilt register.The startdividelogicsig- nal being true then forces the peak detectorto select

the new valueand ignorethe numberin the shift regis- ter.

The peak/averageselector. a multiplexer,selects either the peak or average value to b€ routed to the memories under conrol ot the PK/AVG signal. The selectoroutput is routed throughthe Max Hold circuit. which functionslike the p€ak detector.Whenthe MAX HOLDsignalis high,the valuethat is routedto the out- put multiplexeris the larger of two values:the current memory value at the subject X coordinate or the previously-selectedpeak or averagevalue.

Timingto set up the divideoperationand clearthe numerator,denominator,and peak circuit is controlled by a 1O-stagecountEr.Taps are takenfrom appropriate sfagesto developthe necessaryclearand latchtiming puls€s.

All dataentersand leavesth€ mgmoryserially.Data read from memory enters an 8-bit shift registerand, timed by the SYNCsignal,is transferredto the vertical displayoutput latch (displayregister). The same shift registeris used for other purposes,so the DSPL EN (displayenable)signalpreventsnon-displayinformation from beingtransferredto the outputlatches.An exam- ple of data movingthroughthis shift registeris sEenin the B-Save A display mode.The A valueis first read lrom memoryand stored in the shift register.As the B value is read, the subtractionis done seriallyand the answ€r is appliedto the shift register.Sincethe sub- tractionmustbe perforrnedwith the leastsigniticantbit first, a set of exclusive-ORgates changethe order of extractingB lrom memory.The shiftregisterdirectionis reversed to present th€ most signiftcantbit to the proper display latch. The shift registeroutput is also appliedto the outputmultiplexer.

In subtraction,the operationperformedby the serial calculatoris not merelyB minusA. The actualexpres- sion implementedis (B-A) + K, where K is a serial input externalconstantspecifiedby the user.This per- mits zero to be placed anywhereon the screen.To avoidconfusionwhen(B-A) + K resultsin an off-screen position,the subtractor blanks the display.(Ihe sub- tractor examinesthe carry bit and borrowbit whenthe most significantbit is calculated.lf eitherbit is a 1, the screenis blanked.)

Whenthe Save A mode is not selectedand both A and B are being displayed, maximum resolutionis obtained(1000points acrossthe display)lf. this display includEsa very narrow pulse,it is possiblethat the top of the pulseis only as wide as a singleX coordinate.lf this maximumvaluewere in the B Tableandthe SaveA rnodewas selectedand B turnedoff,therewouldbe an apparentdrop in amplitude.So, whenthe SaveA mode is selected,a specialset of circuitsin U2030compares all A and B values that have the same X value,and stores the larger in Table A. The B value is read and

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