Hardware Design
3.0General Hardware Design Considerations
This chapter contains information for implementing and interfacing with major hardware blocks of the Intel® IXP43X Product Line of Network Processors. Such blocks include DDRII/I SDRAM, Flash, Ethernet PHYs, UART and other peripherals interfaces. Signal definition tables list resistor recommendations for
Features disabled by a specific part number, do not require
Warning: With the exception of USB_V5REF all other I/O pins of the IXP43X network processors are not
Table 2 gives the legend for interpreting the Type field used in the
Table 2. Signal Type Definitions
Symbol | Description |
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I | Input pin only |
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O | Output pin only |
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I/O | Pin can be an input or output |
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OD | |
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TRI | |
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PWR | Power pin |
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GND | Ground pin |
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3.1Soft Fusible Features
Soft Fuse Enable/Disable is a method to enable or disable features in hardware, virtually disconnecting the hardware modules from the processor.
Some of the features offered in the IXP43X product line of network processors can be Soft Fuse Enabled/Disabled during boot. It is recommended that if a feature is not used in the design, the feature be soft disabled. This helps reduce power and maintain the part running at a cooler temperature. When Soft Fuse Disabled, a
Soft Fuse Enable/Disable can be done by writing to EXP_UNIT_FUSE_RESET register. For more information refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual and review the register description.
Table 3. | Soft Fusible Features (Sheet 1 of 2) |
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| PCI | The complete bus must be enabled or disable. |
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| HSS0 | Can only be disable as a pair. |
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| UTOPIA | while enabling UTOPIA, MACs on NPE A is disabled. |
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| while enabling MACs on NPE A, UTOPIA is disabled. |
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| Intel® IXP43X Product Line of Network Processors | |
April 2007 |
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| HDG |
Document Number: 316844; Revision: 001US | 17 |