Intel IXP43X manual Clav, Utpipfci, Utpipsoc, ETHARXDATA30 Etharxclk, UTPIPDATA4

Page 39

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

 

 

Type

Pull

 

 

Name

Up/

Description

 

Field

 

 

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Input Data flow control input signal. Also known as RXEMPTY/

 

 

 

 

CLAV.

 

 

 

 

Used to inform the processor of the ability of each polled PHY to send a complete

 

 

 

 

cell. For cell-level flow control in an MPHY environment, RxClav is an active high

 

 

 

 

tri-stateable signal from the MPHY to ATM layer. The UTP_IP_FCI, which is

 

 

 

 

connected to multiple MPHY devices, sees logic high generated by the PHY, one

 

 

 

 

clock after the given PHY address is asserted, when a full cell can be received by

 

 

 

 

the PHY. The UTP_IP_FCI sees a logic low generated by the PHY, one clock cycle

UTP_IP_FCI

I

Yes

after the PHY address is asserted if a full cell cannot be received by the PHY.

 

 

 

 

In a SPHY mode, this signal is used to indicate to the processor that the PHY has

 

 

 

 

an octet or cell available for transferring to the processor.

 

 

 

 

When this interface/signal is enabled and is not being used in a system design,

 

 

 

 

the interface/signal should be pulled high with a 10-KΩresistor. When this

 

 

 

 

interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft

 

 

 

 

fuse (refer to Expansion Bus Controller chapter of the Intel® IXP43X Product Line

 

 

 

 

of Network Processors Developer’s Manual) and is not being used in a system

 

 

 

 

design, the interface/signal is not required for any connection.

 

 

 

 

 

 

 

 

 

Start of Cell. RX_SOC

 

 

 

 

Active-high signal that is asserted when UTP_IP_DATA contains the first valid

 

 

 

 

byte of a transmitted cell.

UTP_IP_SOC

I

Yes

When this interface/signal is enabled and is not being used in a system design,

the interface/signal should be pulled high with a 10KΩ resistor. When this

 

 

 

 

interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft

 

 

 

 

fuse and is not being used in a system design, it is not required for any

 

 

 

 

connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

 

 

 

 

UTOPIA Level 2 input data. Also known as RX_DATA.

 

 

 

 

Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

 

 

 

 

PHY.

 

 

 

 

MII Mode of Operation:

UTP_IP_DATA[3:0] /

I

Yes

Receives data bus from the PHY; asserted synchronously with respect to

ETHA_RXDATA[3:0]

ETHA_RXCLK.

 

 

When the interface/signal is enabled and is not being used in a system design, it

 

 

 

 

 

 

 

 

should be pulled high with a 10KΩ resistor.

 

 

 

 

When the interface is disabled through the UTOPIA Level 2 and/or the NPE-A

 

 

 

 

Ethernet soft fuse and is not being used in a system design, it is not required for

 

 

 

 

any connection. (Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual).

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

 

 

 

 

UTOPIA Level 2 input data. Also known as RX_DATA.

 

 

 

 

Used by to the processor to receive data from an ATM UTOPIA Level 2-compliant

 

 

 

 

PHY.

 

 

 

 

MII Mode of Operation:

 

 

 

 

Receive data valid used to inform the MII interface about data that is being sent

UTP_IP_DATA[4] /

I

Yes

by the Ethernet PHY.

ETHA_RXDV

This MAC does not contain hardware hashing capabilities that are local to the

 

 

 

 

 

 

interface.

 

 

 

 

When the interface/signal is enabled and is not being used in a system design,

 

 

 

 

the interface/signal should be pulled high with a 10-KΩresistor. When this

 

 

 

 

interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft

 

 

 

 

fuse (and is not being used in a system design, it is not required for any

 

 

 

 

connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

††

Refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an

 

interface.

 

 

 

 

 

 

 

 

 

Intel® IXP43X Product Line of Network Processors

April 2007

HDG

Document Number: 316844; Revision: 001US

39

Page 38 Page 40
Image 39
Page 38 Page 40
Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content OverviewTerm Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1List of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram InterfaceName Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 TypeDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio InterfaceGpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40ETHARXDATA30 Etharxclk ClavUtpipfci UtpipsocUTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7Device Connection HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 PciintanType Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations§ § Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramDcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / DdrrasnDDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram ConfigurationsTechnology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select TotalDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsPrinted Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing RelationshipsSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §
Top Page Image Contents