Intel IXP43X manual High-Speed, Serial Interface, HSSTXDATA0, HSSTXCLK0, HSSRXDATA0, HSSRXCLK0

Page 42

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.9.1Signal Interface

Table 15.

High-Speed, Serial Interface 0

 

 

 

 

 

 

 

Name

 

Type

Pull

 

 

 

Up

Recommendations

 

 

Field

 

 

 

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transmit frame.

HSS_TXFRAME0

 

I/O

Yes

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Transmit data out. Open Drain Output.

HSS_TXDATA0

 

OD

Yes

When this interface/signal is enabled and is used or not used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor to Vcc33.

 

 

 

 

 

 

 

 

 

 

 

Transmit clock.

HSS_TXCLK0

 

I/O

Yes

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Receive frame.

HSS_RXFRAME0

 

I/O

Yes

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Receive data input.

HSS_RXDATA0

 

I

Yes

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

 

 

Receive clock.

HSS_RXCLK0

 

I/O

Yes

When this interface/signal is enabled and is not being used in a system design, the

 

 

 

 

 

interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

Notes:

 

 

 

 

 

1.

Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

 

being disabled without asserting a system reset.

2.

Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

 

unconnected.

 

 

3.

Features Enabled by a specific part number and required to be Soft Fuse-disabled, as stated in Note 1 alone require pull-

 

ups or pull-downs in the clock-input signals.

 

 

 

 

 

 

3.9.2Device Connection

Figure 11 shows a typical interface between the IXP43X network processors and a SLIC CODEC, through the SSP and HSS ports, and a couple of GPIO signals.

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

42

Document Number: 316844; Revision: 001US

Page 41 Page 43
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Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Content Overview Chapter Name DescriptionList of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol DescriptionDDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately EthernetType Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII Gpio Interface MII Interface ExampleGpio Signal Recommendations USB InterfaceDesign Notes USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPADDR40 UTPOPDATA4UTPOPDATA75 UtpopfciUtpipsoc ClavUtpipfci ETHARXDATA30 EtharxclkUTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40HSS Interface Device ConnectionHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 PciclkinPCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection FieldPCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling§ § General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDrasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / DdrcasnDDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations SizeaAddress Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement BanksDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsTiming Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer StackupSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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