Intel IXP43X manual Content Overview, Chapter Name Description

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Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

1.0Introduction

This design guide provides recommendations for hardware and system designers who are developing with the Intel® IXP43X Product Line of Network Processors. This document should be used in conjunction with the Intel® IXP43X Product Line of Network Processors Datasheet and sample schematics provided for the Intel® IXP435 Multi-Service Residential Gateway Reference Platform.

Design recommendations are necessary to meet the timing and signal quality specifications. The guidelines recommended in this document are based on experience and simulation work done at Intel while developing the Intel® IXP435 Multi-Service Residential Gateway Reference Platform. These recommendations are subject to change.

Note: This document discusses all features supported on the IXP43X product line of network processors. A subset of these features is supported by certain processors in the IXP43X network processors, such as the Intel® IXP432 Network Processor. Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for detailed information on various features listed by processor.

1.1Content Overview

	Chapter Name	Description

	Chapter 1.0, “Introduction”	Conventions used in this manual and related documentation

	Chapter 2.0, “System Architecture”	System architectural block diagram and system memory map

	Chapter 3.0, “General Hardware Design	Graphical representation of most common peripheral interfaces
	Considerations”
	Considerations”

	Chapter 4.0, “General PCB Guide”	General PCB design practice and layer stack-up description

	Chapter 5.0, “General Layout and Routing	More specific layout and routing recommendations for board
	Guide”	designers

	Chapter 6.0, “PCI Interface Design	Board-design recommendations when implementing PCI
	Considerations”	interface

	Chapter 7.0, “DDRII / DDRI SDRAM”	Board-design recommendations when implementing
	Chapter 7.0, “DDRII / DDRI SDRAM”	DDRII/I memory interface
		DDRII/I memory interface

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	9

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Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio InterfaceGpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §