Intel IXP43X manual Signal Package Lengths Sheet 2

Page 81

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 33.

Signal Package Lengths (Sheet 2 of 3)

 

 

 

 

 

 

 

 

 

 

 

Group

Signal Name

Length (mil)

 

Signal Name

Length (mil)

 

 

 

 

 

 

 

 

 

D_CB0 / DDR_CB0

402.94

 

D_CB4 / DDR_CB4

385.50

 

 

 

 

 

 

 

 

 

D_CB1 / DDR_CB1

393.93

 

D_CB5 / DDR_CB5

419.24

 

 

 

 

 

 

 

 

 

D_CB2 / DDR_CB2

377.69

 

D_CB6 / DDR_CB6

398.22

 

 

 

 

 

 

 

 

 

D_CB3 / DDR_CB3

378.47

 

D_CB7 / DDR_CB7

435.03

 

 

 

 

 

 

 

 

 

D_DQ0 / DDR_DQ0

447.57

 

D_DQ16 /

536.32

 

 

 

DDR_DQ16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ1 / DDR_DQ1

449.41

 

D_DQ17 /

569.24

 

 

 

DDR_DQ17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ2 / DDR_DQ2

394.02

 

D_DQ18 /

545.35

 

 

 

DDR_DQ18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ3 / DDR_DQ3

366.03

 

D_DQ19 /

633.70

 

 

 

DDR_DQ19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ4 / DDR_DQ4

449.58

 

D_DQ20 /

604.01

 

 

 

DDR_DQ20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ5 / DDR_DQ5

470.40

 

D_DQ21 /

608.22

 

 

 

DDR_DQ21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ6 / DDR_DQ6

413.35

 

D_DQ22 /

479.46

 

 

 

DDR_DQ22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ7 / DDR_DQ7

384.02

 

D_DQ23 /

555.12

 

 

 

DDR_DQ23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ8 / DDR_DQ8

368.37

 

D_DQ24 /

472.85

 

Data

 

DDR_DQ24

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ9 / DDR_DQ9

399.54

 

D_DQ25 /

475.30

 

 

 

DDR_DQ25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ10/ DDR_DQ10

374.55

 

D_DQ26 /

421.35

 

 

 

DDR_DQ26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ11 / DDR_DQ11

398.20

 

D_DQ27 /

419.04

 

 

 

DDR_DQ27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ12 / DDR_DQ12

396.30

 

D_DQ28 /

480.43

 

 

 

DDR_DQ28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ13 / DDR_DQ13

408.81

 

D_DQ29 /

489.89

 

 

 

DDR_DQ29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ14 / DDR_DQ14

371.03

 

D_DQ30 /

430.18

 

 

 

DDR_DQ30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQ15 / DDR_DQ15

388.23

 

D_DQ31 /

431.50

 

 

 

DDR_DQ31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQS0 /

468.21

 

D_DQS2 /

517.45

 

 

DDR_DQS0

 

DDR_DQS2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DQS1 /

371.60

 

D_DQS3 /

463.84

 

 

DDR_DQS1

 

DDR_DQS3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DM0 / DDR_DM0

410.19

 

D_DQS4 /

653.53

 

 

 

DDR_DQS4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D_DM1 / DDR_DM1

482.30

 

D_DM3 / DDR_DM3

536.80

 

 

 

 

 

 

 

 

 

D_DM2 / DDR_DM2

553.44

 

D_DM4 / DDR_DM4

428.52

 

 

 

 

 

 

 

 

 

D_CKE0 / DDR_CKE0

385.61

 

D_CKE1 / DDR_CKE1

384.34

 

Control

 

 

 

 

 

 

D_CS_N0 /

385.35

 

D_CS_N1 /

421.27

 

 

 

 

 

DDR_CS_N0

 

DDR_CS_N1

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® IXP43X Product Line of Network Processors

April 2007

HDG

Document Number: 316844; Revision: 001US

81

Page 80 Page 82
Image 81
Page 80 Page 82
Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio InterfaceGpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §
Top Page Image Contents