Intel IXP43X manual Jtag Interface, PCI Host/Option Interface Pin Description Sheet 3

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 18.

PCI Host/Option Interface Pin Description (Sheet 3 of 3)

 

 

 

 

 

 

 

 

Type

 

Option

 

Name

 

Device-Pin Connection

Type

Description

 

Field

 

 

 

Field

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Connect PCI_INTA_N output from the

 

Interrupt A

PCI_INTA_N

 

O/D

Option to one of the GPIO input signals

 

This interrupt is generated from the Option to

 

of the Host. The GPIO signal at the

O/D

one of the GPIO inputs to the Host.

 

 

 

Host must be configure as an input

 

On the Host this signal is not used, it should

 

 

 

interrupt level sensitive.

 

be pulled high with a 10-KΩresistor.

 

 

 

 

 

 

 

 

 

Clock must be connected to both

 

 

PCI_CLKIN

 

I

devices. Trace lengths must be

I

Clock input

 

matched. Use point to point clock

 

 

 

 

 

 

 

 

distribution.

 

 

 

 

 

 

 

 

3.11.4Design Notes

•The IXP43X network processors do not support the 5 V PCI signal interface by itself. Only the 3.3 V signal interface is supported without signal level conversion; however, it is possible to interface to 5 V logic while using a voltage level converter.

•The PCI Local Bus Specification, Rev. 2.2 requires that the bus is always parked, as some device is always driving the AD lines. You must use pull-ups on these signals. The specification states that the following control lines should be pulled up:

— FRAME_N

— TRDY_N

— IRDY_N

— DEVSEL_N

— STOP_N

— SERR_N

— PERR_N

— LOCK_N

— INTA_N

— INTB_N

— INTC_N

— INTD_N

•The GPIO pins of the IXP43X network processors can be used by PCI devices on PCI slots to request an interrupt from the processors’ PCI controller.

•PCI_INTA_N is used to request interrupts to external PCI Masters. This signal is an open drain and requires a pull-up resistor.

3.12JTAG Interface

JTAG is the popular name for IEEE standards 1149.1-1990 and 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture, which provides support for:

•Board-level boundary-scan connectivity testing

•Connection to software debugging tools through the JTAG interface

•In-system programming of programmable memory and logic devices on the PCB

The interface is controlled through five dedicated test access port (TAP) pins: TDI, TMS, TCK, nTRST, and TDO, as described in the IEEE 1149.1 standard. The boundary-scan test-logic elements include the TAP pins, TAP controller, instruction register, boundary-scan register, bypass register, device identification register, and data-specific registers. These are described in the Intel® IXP43X Product Line of Network Processors Developer’s Manual.

The IXP43X network processors can be controlled during debug through a JTAG interface to the processor, the debug tools such as the Macraigor Systems Raven*, EPI Majic*, Wind River Systems* visionPROBE*/ visionICE* or various other JTAG tools plug into the JTAG interface through a connector.

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

50

Document Number: 316844; Revision: 001US

Page 49 Page 51
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Page 49 Page 51
Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesApril Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Content Overview Chapter Name DescriptionList of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol DescriptionDDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately EthernetType Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleMII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C Gpio Interface MII Interface ExampleDesign Notes Gpio Signal RecommendationsUSB Interface USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPADDR40 UTPOPDATA4UTPOPDATA75 UtpopfciUtpipsoc ClavUtpipfci ETHARXDATA30 EtharxclkUTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40HSS Interface Device ConnectionHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 PciclkinPCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection FieldPCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorRecommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling§ § General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGACrosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDrasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / DdrcasnDDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations SizeaAddress Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement BanksDDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsTiming Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer StackupTiming Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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