Intel IXP43X manual Tables

Page 5

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

11	HSS Interface Example	42
12	Serial Flash and SSP Port (SPI) Interface Example	44
13	PCI Interface	47
14	Clock Oscillator Interface Example	51
15	Recommended circuit design on PCB for crystal oscillator	52
16	Component Placement on a PCB	56
17	8-Layer Stackup	58
18	6-Layer Stackup	58
19	Signal Changing Reference Planes	60
20	Good Design Practice for VIA Hole Placement	61
21	Poor Design Practice for VIA Placement	61
22	Pad-to-Pad Clearance of Passive Components to a PGA or BGA	62
23	PCI Address/Data Topology	67
24	PCI Clock Topology	68
25	Processor-DDRII/I SDRAM Interface	72
26	DDRII/DDRI RCOMP Pin External Resistor Requirements	74
27	DDRII OCD Pin Requirements	75
28	DDR Clock Timing Waveform	75
29	DDR SDRAM Write Timings	76
30	DDR SDRAM Read Timings	76
31	DDR - Write Preamble/Postamble Duration	77
32	DDRII Clock Simulation Results: CK Signals	82
33	DDRII Data and Control Simulation Results: DQ and DQS signals	83
34	DDRII Command Simulation Results: ADDRESS signals	84
Tables
1	List of Acronyms and Abbreviations	10
2	Signal Type Definitions	17
3	Soft Fusible Features	17
4	DDRII/I SDRAM Interface Pin Description	19
5	Expansion Bus Signal Recommendations	21
6	Boot/Reset Strapping Configuration	22
7	Setting Intel XScale® Processor Operation Speed	24
8	UART Signal Recommendations	27
9	MII NPE A Signal Recommendations	29
10	MII NPE C Signal Recommendations	29
11	MAC Management Signal Recommendations NPE A and NPE C	30
12	GPIO Signal Recommendations	32
13	USB Host Signal Recommendations	33
14	UTOPIA Level 2/MII_A	36
15	High-Speed, Serial Interface 0	41
16	Synchronous Serial Peripheral Port Interface	43
17	PCI Controller	45
18	PCI Host/Option Interface Pin Description	47
19	Synchronous Serial Peripheral Port Interface	50
20	Clock Signals	50
21	Power Supply	52
22	PCI Address/Data Routing Guidelines	67
23	PCI Clock Routing Guidelines	68
24	DDRII/I Signal Groups	71
25	Supported DDRI 32-bit SDRAM Configurations	73
26	Supported DDRII 32-bit SDRAM Configurations	73
27	Supported DDRI 16-bit SDRAM Configurations	73
28	Supported DDRII 16-bit SDRAM Configurations	74
	Intel® IXP43X Product Line of Network Processors
April 2007		HDG
Document Number: 316844; Revision: 001US		5

Image 5

Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsApril Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceMII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C MII Interface Example Gpio InterfaceDesign Notes Gpio Signal RecommendationsUSB Interface Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsCrosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupTiming Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §