Intel IXP43X manual Uart Interface, Flash Interface Example

Page 27

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 4. Flash Interface Example

	EX_DATA[15:0]	EX_DATA[15:0]		DATA[15:0]
	Intel® IXP43X Product			16-Bit Device
	Line of Network			16-Bit Device
	Processors	EX_ADDR[23:0]		16-Bit-Word Access
	EX_ADDR[23:0]	EX_ADDR[23:0]		ADDR[23:0]
	EX_ADDR[23:0]			ADDR[23:0]
	EX_CS_N	CS		CE0
	EX_RD_N	OE		OE_N
	EX_WR_N	WR		WR_N
		3.3 V	RST#	Intel® Flash
			RST#	RP_N
				CE1
	0 KΩ	4.7 KΩ		CE2
				BYTE_N
				VPEN_N
				4.7 KΩ
				B4097- 005

3.4UART Interface

The UART interface are a 16550-compliant UART with the exception of transmit and receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 UART specification.

The interface can be configured to support speeds from 1,200 Baud to 921 Kbaud. The interface supports the following configurations:

•Five, six, seven, or eight data-bit transfers

•One or two stop bits

•Even, odd, or no parity

The request-to-send (RTS0_N) and clear-to-send (CTS0_N) modem control signals also are available with the interface for hardware flow control. The hardware supports a four-wire interface:

•Transmit Data

•Receive Data

•Request to Send

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	27

Image 27

Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content OverviewTerm Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1List of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram InterfaceName Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 TypeDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio InterfaceGpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40ETHARXDATA30 Etharxclk ClavUtpipfci UtpipsocUTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7Device Connection HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 PciintanType Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations§ § Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHzClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramDcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / DdrrasnDDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram ConfigurationsTechnology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select TotalDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsPrinted Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing RelationshipsSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §