Intel IXP43X manual Figures

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

	3.14	Power	..............................................................................................................		52
		3.14.1	Decoupling Capacitance Recommendations		53
		3.14.2	VCC Decoupling		53
		3.14.3	VCC33 Decoupling		53
		3.14.4	VCCDDR Decoupling		53
		3.14.5	Power Sequence		53
		3.14.6	Reset Timing		53
4.0	General PCB Guide				55
	4.1	PCB Overview			55
	4.2	General Recommendations			55
	4.3	Component Selection			55
	4.4	Component Placement			55
	4.5	Stack-Up Selection			56
5.0 General Layout and Routing Guide					59
	5.1	Overview			59
	5.2	General Layout Guidelines			59
		5.2.1	General Component Spacing		60
		5.2.2	Clock Signal Considerations		62
		5.2.3	MII Signal Considerations		63
		5.2.4	USB V2.0 Considerations		63
		5.2.5	Crosstalk		63
		5.2.6	EMI Design Considerations		64
		5.2.7	Trace Impedance		64
		5.2.8	Power and Ground Plane		64
6.0 PCI Interface Design Considerations					66
	6.1	Electrical Interface			66
	6.2	Topology			66
	6.3	Clock Distribution		..............................................................................................	67
		6.3.1	Trace Length Limits		68
		6.3.2	Routing Guidelines		69
		6.3.3	Signal Loading		69
7.0 DDRII / DDRI SDRAM					70
	7.1	Introduction			70
	7.2	DDRII/DDRI RCOMP and Slew Resistances Pin Requirements			74
	7.3	DDRII OCD Pin Requirements			75
		7.3.1	Signal-Timing Analysis		75
		7.3.2	Timing Relationships		78
		7.3.3	Routing Guidelines		81
			7.3.3.1	Clock Group	81
			7.3.3.2 Data and Control Groups		82
			7.3.3.3	Command Groups	84
Figures
1 Intel® IXP435 Network Processor Block Diagram					13
2 Example: Intel® IXP43X Product Line of Network Processors System Block Diagram					16
3	8/16-Bit Device Interface				25
4	Flash Interface Example				26
5	UART Interface Example				28
6	MII Interface Example				31
7	Common Mode Choke				34
8 USB RCOMP and ICOMP Pin Requirement					35
9 USB Host Down Stream Interface Example					35
10	UTOPIA Interface Example				40
Intel® IXP43X Product Line of Network Processors
HDG					April 2007
4				Document Number: 316844; Revision: 001US

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Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesHDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Content Overview Chapter Name DescriptionRelated Documentation AcronymsList of Acronyms and Abbreviations Sheet 1 Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Signal Type DefinitionsSoft Fusible Features Sheet 1 Symbol DescriptionSoft Fusible Features Sheet 2 USB Host Each USB can be Enable separatelyDDRII/I Sdram Interface EthernetSignal Interface DDRII/I Sdram Interface Pin Description Sheet 1Type Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Expansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2Boot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Setting Intel XScale Processor Operation Speed 3 8-Bit Device InterfaceIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleMII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII Gpio Interface MII Interface ExampleUSB Interface Gpio Signal RecommendationsDesign Notes USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down UTPOPDATA4 UTPOPDATA75UTPOPADDR40 UtpopfciClav UtpipfciUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA5 UTPIPDATA6UTPIPDATA7 UTPIPADDR40HSS Interface Device ConnectionHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Pciintan PciclkinConnect signal to same pin between PCI Parity Two devices PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldOn the Option device, these signals are not Signal PCIREQN0 to one PCIREQN30 inputs to the HostPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description Power Sequence Reset TimingDecoupling Capacitance Recommendations VCC Decoupling§ § Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAUSB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Electrical Interface Topology@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDDRII/I Signal Groups Group Signal Name DescriptionDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddri 32-bit Sdram Configurations Supported Ddrii 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaSupported Ddrii 16-bit Sdram Configurations DDRII/DDRI Rcomp and Slew Resistances Pin RequirementsAddress Size Leaf Select Total Technology Arrangement BanksDdrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsDDR II/I Sdram Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum UnitsTiming Relationships Printed Circuit Board Layer StackupGroup Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §